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authorOwen Anderson <resistor@mac.com>2010-09-23 22:44:10 +0000
committerOwen Anderson <resistor@mac.com>2010-09-23 22:44:10 +0000
commit5716180b1a863d345127fa8f9dfe0a931ab7370c (patch)
treea4ef16abce9e17a85b87603a5ba0cae14349546d /utils/TableGen/CodeGenInstruction.cpp
parent823d9a53a426a2612bd73eda610fee75962ebd05 (diff)
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Add an TargetInstrDesc bit to indicate that a given instruction is a conditional move.
Not intended functionality change, as nothing uses this yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114702 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/CodeGenInstruction.cpp')
-rw-r--r--utils/TableGen/CodeGenInstruction.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp
index 01a1fe11f5..b36cf983a5 100644
--- a/utils/TableGen/CodeGenInstruction.cpp
+++ b/utils/TableGen/CodeGenInstruction.cpp
@@ -103,6 +103,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
isBranch = R->getValueAsBit("isBranch");
isIndirectBranch = R->getValueAsBit("isIndirectBranch");
isCompare = R->getValueAsBit("isCompare");
+ isConditionalMove = R->getValueAsBit("isConditionalMove");
isBarrier = R->getValueAsBit("isBarrier");
isCall = R->getValueAsBit("isCall");
canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");