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| author | Bill Wendling <isanbard@gmail.com> | 2010-11-06 19:56:04 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2010-11-06 19:56:04 +0000 |
| commit | 8d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7 (patch) | |
| tree | 6cd1843fd1373f4a178f757fade8ae6f43da13ea /utils/TableGen/CodeGenInstruction.cpp | |
| parent | 98c870f87b7f0c996a9ba67003d88d434d6dbcd0 (diff) | |
| download | llvm-8d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7.tar.gz llvm-8d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7.tar.bz2 llvm-8d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7.tar.xz | |
Add a RegList (register list) object to ARMOperand. It will be used soon to hold
(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118351 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/CodeGenInstruction.cpp')
0 files changed, 0 insertions, 0 deletions