summaryrefslogtreecommitdiff
path: root/utils/TableGen/CodeGenRegisters.cpp
diff options
context:
space:
mode:
authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-03-29 18:03:59 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-03-29 18:03:59 +0000
commitc6a96ff6aeeb77e1007364e5603b72f3ab4cc7bd (patch)
treeba7f8bdab2bb94e030d23ad040a3fa6512a71921 /utils/TableGen/CodeGenRegisters.cpp
parent41e2073f623a08504e2e1e5a9fc5c9f22a03eb83 (diff)
downloadllvm-c6a96ff6aeeb77e1007364e5603b72f3ab4cc7bd.tar.gz
llvm-c6a96ff6aeeb77e1007364e5603b72f3ab4cc7bd.tar.bz2
llvm-c6a96ff6aeeb77e1007364e5603b72f3ab4cc7bd.tar.xz
Add more constness to CodeGenRegisters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153667 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/CodeGenRegisters.cpp')
-rw-r--r--utils/TableGen/CodeGenRegisters.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp
index 9c61f3f7df..d86ca7a282 100644
--- a/utils/TableGen/CodeGenRegisters.cpp
+++ b/utils/TableGen/CodeGenRegisters.cpp
@@ -231,7 +231,7 @@ CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
}
void
-CodeGenRegister::addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet,
+CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
CodeGenRegBank &RegBank) const {
assert(SubRegsComplete && "Must precompute sub-registers");
std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
@@ -1095,7 +1095,7 @@ CodeGenRegBank::getRegClassForRegister(Record *R) {
}
BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
- SetVector<CodeGenRegister*> Set;
+ SetVector<const CodeGenRegister*> Set;
// First add Regs with all sub-registers.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
@@ -1110,7 +1110,7 @@ BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
for (unsigned i = 0; i != Set.size(); ++i) {
const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs();
for (unsigned j = 0, e = SR.size(); j != e; ++j) {
- CodeGenRegister *Super = SR[j];
+ const CodeGenRegister *Super = SR[j];
if (!Super->CoveredBySubRegs || Set.count(Super))
continue;
// This new super-register is covered by its sub-registers.