Compute lists of super-classes in CodeGenRegisterClass.

Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140895 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 10 insertions, 0 deletions

diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp
index c712495012..35f247a2e3 100644
--- a/utils/TableGen/CodeGenRegisters.cpp
+++ b/utils/TableGen/CodeGenRegisters.cpp
@@ -414,6 +414,16 @@ computeSubClasses(ArrayRef<CodeGenRegisterClass*> RegClasses) {
     for (unsigned s = rci - 1; s && RC.hasSubClass(RegClasses[s - 1]); --s)
       RC.SubClasses.set(s - 1);
   }
+
+  // Compute the SuperClasses lists from the SubClasses vectors.
+  for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
+    const BitVector &SC = RegClasses[rci]->getSubClasses();
+    for (int s = SC.find_first(); s >= 0; s = SC.find_next(s)) {
+      if (unsigned(s) == rci)
+        continue;
+      RegClasses[s]->SuperClasses.push_back(RegClasses[rci]);
+    }
+  }
 }
 
 //===----------------------------------------------------------------------===//