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| author | Christopher Lamb <christopher.lamb@gmail.com> | 2008-03-13 05:47:01 +0000 |
|---|---|---|
| committer | Christopher Lamb <christopher.lamb@gmail.com> | 2008-03-13 05:47:01 +0000 |
| commit | 6634e26aa11b0e2eabde8b3b463bb943364f8d9d (patch) | |
| tree | f6acb329d49272da4adec8fba66734bba41760b5 /utils/TableGen/DAGISelEmitter.cpp | |
| parent | 3bdfa04cbe42106d2dc55d0dd980ba9e52a3bd84 (diff) | |
| download | llvm-6634e26aa11b0e2eabde8b3b463bb943364f8d9d.tar.gz llvm-6634e26aa11b0e2eabde8b3b463bb943364f8d9d.tar.bz2 llvm-6634e26aa11b0e2eabde8b3b463bb943364f8d9d.tar.xz | |
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/DAGISelEmitter.cpp')
| -rw-r--r-- | utils/TableGen/DAGISelEmitter.cpp | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index 291a913c37..0c6afab4c9 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -975,9 +975,9 @@ public: } } - // Generate MemOperandSDNodes nodes for each memory accesses covered by this - // pattern. - if (isRoot) { + // Generate MemOperandSDNodes nodes for each memory accesses covered by + // this pattern. + if (II.isSimpleLoad | II.mayLoad | II.mayStore) { std::vector<std::string>::const_iterator mi, mie; for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) { emitCode("SDOperand LSI_" + *mi + " = " @@ -1880,14 +1880,9 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) { << " SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n" << " AddToISelQueue(N1);\n" << " SDOperand Ops[] = { N0, N1, Tmp };\n" - << " if (N0.getOpcode() == ISD::UNDEF) {\n" - << " return CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG,\n" - << " N.getValueType(), Ops+1, 2);\n" - << " } else {\n" - << " AddToISelQueue(N0);\n" - << " return CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG,\n" - << " N.getValueType(), Ops, 3);\n" - << " }\n" + << " AddToISelQueue(N0);\n" + << " return CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG,\n" + << " N.getValueType(), Ops, 3);\n" << "}\n\n"; OS << "// The main instruction selector code.\n" |