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authorChris Lattner <sabre@nondot.org>2010-03-19 05:34:15 +0000
committerChris Lattner <sabre@nondot.org>2010-03-19 05:34:15 +0000
commit1e50631675df50a0701ef8b527ced63d0d535a81 (patch)
tree3ca720600c5e27ab04a6ef7bc2a6aac94281c548 /utils/TableGen/DAGISelMatcherGen.cpp
parent60e9eac357dc6e6d9396f02b171baf9e70d97649 (diff)
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resolve fixme: we now infer the instruction-level 'isvariadic' bit
from the pattern if present, and we use it instead of the bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98938 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/DAGISelMatcherGen.cpp')
-rw-r--r--utils/TableGen/DAGISelMatcherGen.cpp10
1 files changed, 5 insertions, 5 deletions
diff --git a/utils/TableGen/DAGISelMatcherGen.cpp b/utils/TableGen/DAGISelMatcherGen.cpp
index d093837829..0c0b7265e5 100644
--- a/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/utils/TableGen/DAGISelMatcherGen.cpp
@@ -734,12 +734,12 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
}
}
- // FIXME2: Instead of using the isVariadic flag on the instruction, we should
- // have an SDNP that indicates variadicism. The TargetInstrInfo isVariadic
- // property should be inferred from this when an instruction has a pattern.
+ // If this is the root of the pattern and the pattern we're matching includes
+ // a node that is variadic, mark the generated node as variadic so that it
+ // gets the excess operands from the input DAG.
int NumFixedArityOperands = -1;
- if (N->NodeHasProperty(SDNPVariadic, CGP) ||
- (isRoot && II.isVariadic))
+ if (isRoot &&
+ (Pattern.getSrcPattern()->NodeHasProperty(SDNPVariadic, CGP)))
NumFixedArityOperands = Pattern.getSrcPattern()->getNumChildren();
// If this is the root node and any of the nodes matched nodes in the input