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| author | Jim Grosbach <grosbach@apple.com> | 2011-08-03 23:50:40 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-08-03 23:50:40 +0000 |
| commit | 7ce057983ea7b8ad42d5cca1bb5d3f6941662269 (patch) | |
| tree | 54a731f5142d082ed12dd47c2c4625ed0eb68619 /utils/TableGen/EDEmitter.cpp | |
| parent | 762797d1af1b9308c79982aedd9bd2f585f46171 (diff) | |
| download | llvm-7ce057983ea7b8ad42d5cca1bb5d3f6941662269.tar.gz llvm-7ce057983ea7b8ad42d5cca1bb5d3f6941662269.tar.bz2 llvm-7ce057983ea7b8ad42d5cca1bb5d3f6941662269.tar.xz | |
ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/EDEmitter.cpp')
| -rw-r--r-- | utils/TableGen/EDEmitter.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp index c262633bf2..e7dba13984 100644 --- a/utils/TableGen/EDEmitter.cpp +++ b/utils/TableGen/EDEmitter.cpp @@ -613,6 +613,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type, IMM("shr_imm32"); IMM("shr_imm64"); IMM("t2ldrlabel"); + IMM("postidx_imm8"); MISC("brtarget", "kOperandTypeARMBranchTarget"); // ? MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ? @@ -639,9 +640,10 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type, MISC("it_pred", "kOperandTypeARMPredicate"); // I MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I + MISC("postidx_reg", "kOperandTypeARMAddrMode3Offset"); // R, I MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I - MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset"); // R, I - MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset"); // R, I + MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset"); // R, I + MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset"); // R, I MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I |