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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-04-30 21:22:44 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-04-30 21:22:44 +0000 |
commit | 7afcc6aa270ca51e502de9f826ecdf61568a73b9 (patch) | |
tree | b69b86fe2a0bc09cdfe09cf92cde407fa9369eda /utils/TableGen/RegisterInfoEmitter.cpp | |
parent | 3d739fe3756bf67be23c2ca54ec7b04bef89bfe0 (diff) | |
download | llvm-7afcc6aa270ca51e502de9f826ecdf61568a73b9.tar.gz llvm-7afcc6aa270ca51e502de9f826ecdf61568a73b9.tar.bz2 llvm-7afcc6aa270ca51e502de9f826ecdf61568a73b9.tar.xz |
Slightly change TableGen's definition of a register subclass.
A subclass is allowed to have a larger spill size than the superclass, and the
spill alignment must be a multiple of the superclass alignment. This causes
the following new subclass relations:
=== Alpha ===
F4RC -> F8RC
=== PPC ===
F4RC -> F8RC
=== SPU ===
R8C -> R16C -> R32C/R32FP -> R64C/R64FP -> GPRC/VECREG
=== X86 ===
FR32 -> FR64 -> VR128
RFP32 -> RFP64 -> RFP80
These subclass relations are consistent with the behaviour of -join-cross-class-copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70511 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/RegisterInfoEmitter.cpp')
-rw-r--r-- | utils/TableGen/RegisterInfoEmitter.cpp | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 3c3b2e8ff4..dcf965cc1d 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -340,8 +340,21 @@ void RegisterInfoEmitter::run(std::ostream &OS) { bool Empty = true; for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; + + // RC2 is a sub-class of RC if it is a valid replacement for any + // instruction operand where an RC register is required. It must satisfy + // these conditions: + // + // 1. All RC2 registers are also in RC. + // 2. The RC2 spill size must not be smaller that the RC spill size. + // 3. RC2 spill alignment must be compatible with RC. + // + // Sub-classes are used to determine if a virtual register can be used + // as an instruction operand, or if it must be copied first. + if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() || - RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet)) + (RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) || + RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet)) continue; if (!Empty) OS << ", "; |