Initial checkin of the new "fast" instruction selection support. See

the comments in FastISelEmitter.cpp for details on what this is.
This is currently experimental and unusable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54751 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 7 insertions, 0 deletions

diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index 64b2f97dc3..d6e84609f4 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -29,6 +29,7 @@
 #include "InstrEnumEmitter.h"
 #include "AsmWriterEmitter.h"
 #include "DAGISelEmitter.h"
+#include "FastISelEmitter.h"
 #include "SubtargetEmitter.h"
 #include "IntrinsicEmitter.h"
 #include "LLVMCConfigurationEmitter.h"
@@ -45,6 +46,7 @@ enum ActionType {
   GenInstrEnums, GenInstrs, GenAsmWriter,
   GenCallingConv,
   GenDAGISel,
+  GenFastISel,
   GenSubtarget,
   GenIntrinsic,
   GenLLVMCConf,
@@ -74,6 +76,8 @@ namespace {
                                "Generate assembly writer"),
                     clEnumValN(GenDAGISel, "gen-dag-isel",
                                "Generate a DAG instruction selector"),
+                    clEnumValN(GenFastISel, "gen-fast-isel",
+                               "Generate a \"fast\" instruction selector"),
                     clEnumValN(GenSubtarget, "gen-subtarget",
                                "Generate subtarget enumerations"),
                     clEnumValN(GenIntrinsic, "gen-intrinsic",
@@ -177,6 +181,9 @@ int main(int argc, char **argv) {
     case GenDAGISel:
       DAGISelEmitter(Records).run(*Out);
       break;
+    case GenFastISel:
+      FastISelEmitter(Records).run(*Out);
+      break;
     case GenSubtarget:
       SubtargetEmitter(Records).run(*Out);
       break;