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| author | Sean Callanan <scallanan@apple.com> | 2010-05-06 20:59:00 +0000 |
|---|---|---|
| committer | Sean Callanan <scallanan@apple.com> | 2010-05-06 20:59:00 +0000 |
| commit | 1a8b789a4b8290d263c1c75411788ca45bae3230 (patch) | |
| tree | d18bc584208f7d70eab776d4584100cf3541febf /utils/TableGen | |
| parent | a5d0b54ec156dd31a77a7994e9552a562cd2bf8c (diff) | |
| download | llvm-1a8b789a4b8290d263c1c75411788ca45bae3230.tar.gz llvm-1a8b789a4b8290d263c1c75411788ca45bae3230.tar.bz2 llvm-1a8b789a4b8290d263c1c75411788ca45bae3230.tar.xz | |
Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen')
| -rw-r--r-- | utils/TableGen/EDEmitter.cpp | 3 | ||||
| -rw-r--r-- | utils/TableGen/X86RecognizableInstr.cpp | 6 |
2 files changed, 3 insertions, 6 deletions
diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp index dd0924f99c..406c48a5e5 100644 --- a/utils/TableGen/EDEmitter.cpp +++ b/utils/TableGen/EDEmitter.cpp @@ -309,8 +309,7 @@ static int X86TypeFromOpName(LiteralConstantEmitter *type, REG("RST"); REG("SEGMENT_REG"); REG("DEBUG_REG"); - REG("CONTROL_REG_32"); - REG("CONTROL_REG_64"); + REG("CONTROL_REG"); IMM("i8imm"); IMM("i16imm"); diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index b15db2fab0..94ed15b0c3 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -835,8 +835,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("opaque512mem", TYPE_M512) TYPE("SEGMENT_REG", TYPE_SEGMENTREG) TYPE("DEBUG_REG", TYPE_DEBUGREG) - TYPE("CONTROL_REG_32", TYPE_CR32) - TYPE("CONTROL_REG_64", TYPE_CR64) + TYPE("CONTROL_REG", TYPE_CONTROLREG) TYPE("offset8", TYPE_MOFFS8) TYPE("offset16", TYPE_MOFFS16) TYPE("offset32", TYPE_MOFFS32) @@ -895,8 +894,7 @@ OperandEncoding RecognizableInstr::roRegisterEncodingFromString ENCODING("VR64", ENCODING_REG) ENCODING("SEGMENT_REG", ENCODING_REG) ENCODING("DEBUG_REG", ENCODING_REG) - ENCODING("CONTROL_REG_32", ENCODING_REG) - ENCODING("CONTROL_REG_64", ENCODING_REG) + ENCODING("CONTROL_REG", ENCODING_REG) errs() << "Unhandled reg/opcode register encoding " << s << "\n"; llvm_unreachable("Unhandled reg/opcode register encoding"); } |