diff options
author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-05-04 03:30:28 +0000 |
---|---|---|
committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-05-04 03:30:28 +0000 |
commit | 7855ec62c3b6b5b7e6d3fada589511abd964fdb3 (patch) | |
tree | b2aba05a24773b28bc632a42c5c2dc8fc61fefe7 /utils/TableGen | |
parent | 18efed7adc79c1970f307bb5b015d199012ba872 (diff) | |
download | llvm-7855ec62c3b6b5b7e6d3fada589511abd964fdb3.tar.gz llvm-7855ec62c3b6b5b7e6d3fada589511abd964fdb3.tar.bz2 llvm-7855ec62c3b6b5b7e6d3fada589511abd964fdb3.tar.xz |
Remove TargetRegisterClass::SuperRegClasses.
This manually enumerated list of super-register classes has been
superceeded by the automatically computed super-register class masks
available through SuperRegClassIterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156151 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen')
-rw-r--r-- | utils/TableGen/CodeGenRegisters.cpp | 23 | ||||
-rw-r--r-- | utils/TableGen/CodeGenRegisters.h | 2 | ||||
-rw-r--r-- | utils/TableGen/RegisterInfoEmitter.cpp | 51 |
3 files changed, 0 insertions, 76 deletions
diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp index 45c5bb8b3a..a9eed98a5b 100644 --- a/utils/TableGen/CodeGenRegisters.cpp +++ b/utils/TableGen/CodeGenRegisters.cpp @@ -505,29 +505,6 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) } } - // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags. - ListInit *SRC = R->getValueAsListInit("SubRegClasses"); - for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) { - DagInit *DAG = dynamic_cast<DagInit*>(*i); - if (!DAG) throw "SubRegClasses must contain DAGs"; - DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator()); - Record *RCRec; - if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass")) - throw "Operator '" + DAG->getOperator()->getAsString() + - "' in SubRegClasses is not a RegisterClass"; - // Iterate over args, all SubRegIndex instances. - for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end(); - ai != ae; ++ai) { - DefInit *Idx = dynamic_cast<DefInit*>(*ai); - Record *IdxRec; - if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex")) - throw "Argument '" + (*ai)->getAsString() + - "' in SubRegClasses is not a SubRegIndex"; - if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second) - throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice"; - } - } - // Allow targets to override the size in bits of the RegisterClass. unsigned Size = R->getValueAsInt("Size"); diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index 232a6e71de..dfe5e62b17 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -197,8 +197,6 @@ namespace llvm { unsigned SpillAlignment; int CopyCost; bool Allocatable; - // Map SubRegIndex -> RegisterClass - DenseMap<Record*,Record*> SubRegClasses; std::string AltOrderSelect; // Return the Record that defined this class, or NULL if the class was diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 6c21032233..5b4a876e1b 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -776,58 +776,9 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, // Now that all of the structs have been emitted, emit the instances. if (!RegisterClasses.empty()) { - std::map<unsigned, std::set<unsigned> > SuperRegClassMap; - OS << "\nstatic const TargetRegisterClass *const " << "NullRegClasses[] = { NULL };\n\n"; - unsigned NumSubRegIndices = RegBank.getSubRegIndices().size(); - - if (NumSubRegIndices) { - // Compute the super-register classes for each RegisterClass - for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { - const CodeGenRegisterClass &RC = *RegisterClasses[rc]; - for (DenseMap<Record*,Record*>::const_iterator - i = RC.SubRegClasses.begin(), - e = RC.SubRegClasses.end(); i != e; ++i) { - // Find the register class number of i->second for SuperRegClassMap. - const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second); - assert(RC2 && "Invalid register class in SubRegClasses"); - SuperRegClassMap[RC2->EnumValue].insert(rc); - } - } - - // Emit the super-register classes for each RegisterClass - for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { - const CodeGenRegisterClass &RC = *RegisterClasses[rc]; - - // Give the register class a legal C name if it's anonymous. - std::string Name = RC.getName(); - - OS << "// " << Name - << " Super-register Classes...\n" - << "static const TargetRegisterClass *const " - << Name << "SuperRegClasses[] = {\n "; - - bool Empty = true; - std::map<unsigned, std::set<unsigned> >::iterator I = - SuperRegClassMap.find(rc); - if (I != SuperRegClassMap.end()) { - for (std::set<unsigned>::iterator II = I->second.begin(), - EE = I->second.end(); II != EE; ++II) { - const CodeGenRegisterClass &RC2 = *RegisterClasses[*II]; - if (!Empty) - OS << ", "; - OS << "&" << RC2.getQualifiedName() << "RegClass"; - Empty = false; - } - } - - OS << (!Empty ? ", " : "") << "NULL"; - OS << "\n};\n\n"; - } - } - // Emit register class bit mask tables. The first bit mask emitted for a // register class, RC, is the set of sub-classes, including RC itself. // @@ -946,8 +897,6 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, OS << "NullRegClasses,\n "; else OS << RC.getName() << "Superclasses,\n "; - OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null")) - << "RegClasses,\n "; if (RC.AltOrderSelect.empty()) OS << "0\n"; else |