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| author | Andrew Trick <atrick@apple.com> | 2013-09-25 18:14:12 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-09-25 18:14:12 +0000 |
| commit | 070156437752179833b1e5fddd50caa03fd7c12f (patch) | |
| tree | 51f3737749c059861d132cc0390b8693fb908136 /utils | |
| parent | 2558c2bfbaa4bfd49ee8e06be78a0ccb0f3ff0e7 (diff) | |
| download | llvm-070156437752179833b1e5fddd50caa03fd7c12f.tar.gz llvm-070156437752179833b1e5fddd50caa03fd7c12f.tar.bz2 llvm-070156437752179833b1e5fddd50caa03fd7c12f.tar.xz | |
Mark the x86 machine model as incomplete. PR17367.
Ideally, the machinel model is added at the time the instructions are
defined. But many instructions in X86InstrSSE.td still need a model.
Without this workaround the scheduler asserts because x86 already has
itinerary classes for these instructions, indicating they should be
modeled by the scheduler. Since we use the new machine model for other
instructions, it expects a new machine model for these too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191391 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
| -rw-r--r-- | utils/TableGen/SubtargetEmitter.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp index 81bb6f8fd4..b9f9d06039 100644 --- a/utils/TableGen/SubtargetEmitter.cpp +++ b/utils/TableGen/SubtargetEmitter.cpp @@ -1198,6 +1198,11 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ','); EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ','); EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ','); + + OS << " " << (bool)(PI->ModelDef ? + PI->ModelDef->getValueAsBit("CompleteModel") : 0) + << ", // " << "CompleteModel\n"; + OS << " " << PI->Index << ", // Processor ID\n"; if (PI->hasInstrSchedModel()) OS << " " << PI->ModelName << "ProcResources" << ",\n" |