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| author | Chris Lattner <sabre@nondot.org> | 2010-06-05 04:17:30 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-06-05 04:17:30 +0000 |
| commit | 1087f54ddb70bd2a7ab62608161e4a3f0c345935 (patch) | |
| tree | dc95c8cba3a2dd08aa0facb0293c7689bca5e6bb /utils | |
| parent | 3eca98bb3ab1ec27ab8763298c416d282cdaa261 (diff) | |
| download | llvm-1087f54ddb70bd2a7ab62608161e4a3f0c345935.tar.gz llvm-1087f54ddb70bd2a7ab62608161e4a3f0c345935.tar.bz2 llvm-1087f54ddb70bd2a7ab62608161e4a3f0c345935.tar.xz | |
revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
| -rw-r--r-- | utils/TableGen/X86RecognizableInstr.cpp | 8 | ||||
| -rw-r--r-- | utils/TableGen/X86RecognizableInstr.h | 2 |
2 files changed, 1 insertions, 9 deletions
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index 5fe2bfec1d..b7085ae6c7 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -212,7 +212,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix"); HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); - HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix"); HasLockPrefix = Rec->getValueAsBit("hasLockPrefix"); IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); @@ -533,12 +532,7 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { "Unexpected number of operands for MRMSrcRegFrm"); HANDLE_OPERAND(roRegister) HANDLE_OPERAND(rmRegister) - - if (HasVEX_4VPrefix) - // FIXME: encoding of registers in AVX is in 1's complement form. - HANDLE_OPTIONAL(rmRegister) - else - HANDLE_OPTIONAL(immediate) + HANDLE_OPTIONAL(immediate) break; case X86Local::MRMSrcMem: // Operand 1 is a register operand in the Reg/Opcode field. diff --git a/utils/TableGen/X86RecognizableInstr.h b/utils/TableGen/X86RecognizableInstr.h index db4d96dda0..84374b000b 100644 --- a/utils/TableGen/X86RecognizableInstr.h +++ b/utils/TableGen/X86RecognizableInstr.h @@ -52,8 +52,6 @@ private: bool HasOpSizePrefix; /// The hasREX_WPrefix field from the record bool HasREX_WPrefix; - /// The hasVEX_4VPrefix field from the record - bool HasVEX_4VPrefix; /// The hasLockPrefix field from the record bool HasLockPrefix; /// The isCodeGenOnly filed from the record |