Remove trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21428 91177308-0d34-0410-b5e6-96231b3b80d8

20 files changed, 136 insertions, 136 deletions

diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp
index 9b492bc417..41ecc40069 100644
--- a/utils/TableGen/AsmWriterEmitter.cpp
+++ b/utils/TableGen/AsmWriterEmitter.cpp
@@ -1,10 +1,10 @@
 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend is emits an assembly printer for the current target.
@@ -64,7 +64,7 @@ namespace {
   struct AsmWriterInst {
     std::vector<AsmWriterOperand> Operands;
     const CodeGenInstruction *CGI;
-    
+
     AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant);
 
     /// MatchesAllButOneOp - If this instruction is exactly identical to the
@@ -198,7 +198,7 @@ unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{
     if (Operands[i] != Other.Operands[i])
       if (MismatchOperand != ~0U)  // Already have one mismatch?
         return ~1U;
-      else 
+      else
         MismatchOperand = i;
   }
   return MismatchOperand;
@@ -268,7 +268,7 @@ static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
       OpsToPrint.push_back(std::make_pair(Namespace+"::"+
                                           FirstInst.CGI->TheDef->getName(),
                                           FirstInst.Operands[i]));
-                                          
+
       for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
         AsmWriterInst &AWI = SimilarInsts[si];
         OpsToPrint.push_back(std::make_pair(Namespace+"::"+
@@ -313,7 +313,7 @@ void AsmWriterEmitter::run(std::ostream &O) {
 
   // If all of the instructions start with a constant string (a very very common
   // occurance), emit all of the constant strings as a big table lookup instead
-  // of requiring a switch for them.  
+  // of requiring a switch for them.
   bool AllStartWithString = true;
 
   for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
@@ -323,7 +323,7 @@ void AsmWriterEmitter::run(std::ostream &O) {
       AllStartWithString = false;
       break;
     }
-  
+
   if (AllStartWithString) {
     // Compute the CodeGenInstruction -> AsmWriterInst mapping.  Note that not
     // all machine instructions are necessarily being printed, so there may be
@@ -361,7 +361,7 @@ void AsmWriterEmitter::run(std::ostream &O) {
 
   O << "  switch (MI->getOpcode()) {\n"
        "  default: return false;\n";
-  
+
   while (!Instructions.empty())
     EmitInstructions(Instructions, O);
 
diff --git a/utils/TableGen/AsmWriterEmitter.h b/utils/TableGen/AsmWriterEmitter.h
index 42d070ec75..155dfc83c0 100644
--- a/utils/TableGen/AsmWriterEmitter.h
+++ b/utils/TableGen/AsmWriterEmitter.h
@@ -1,10 +1,10 @@
 //===- AsmWriterEmitter.h - Generate an assembly writer ---------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend is responsible for emitting an assembly printer for the
@@ -23,7 +23,7 @@ namespace llvm {
     RecordKeeper &Records;
   public:
     AsmWriterEmitter(RecordKeeper &R) : Records(R) {}
-    
+
     // run - Output the asmwriter, returning true on failure.
     void run(std::ostream &o);
   };
diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp
index a9e8261e25..6365880124 100644
--- a/utils/TableGen/CodeEmitterGen.cpp
+++ b/utils/TableGen/CodeEmitterGen.cpp
@@ -1,10 +1,10 @@
 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // CodeEmitterGen uses the descriptions of instructions and their fields to
@@ -112,7 +112,7 @@ void CodeEmitterGen::run(std::ostream &o) {
       }
       BI = NewBI;
     }
- 
+
     unsigned Value = 0;
     const std::vector<RecordVal> &Vals = R->getValues();
 
@@ -130,16 +130,16 @@ void CodeEmitterGen::run(std::ostream &o) {
 
     DEBUG(o << "      // " << *R->getValue("Inst") << "\n");
     o << "      Value = " << Value << "U;\n\n";
-    
+
     // Loop over all of the fields in the instruction, determining which are the
-    // operands to the instruction. 
+    // operands to the instruction.
     unsigned op = 0;
     std::map<std::string, unsigned> OpOrder;
     std::map<std::string, bool> OpContinuous;
     for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
       if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
         // Is the operand continuous? If so, we can just mask and OR it in
-        // instead of doing it bit-by-bit, saving a lot in runtime cost.        
+        // instead of doing it bit-by-bit, saving a lot in runtime cost.
         BitsInit *InstInit = BI;
         int beginBitInVar = -1, endBitInVar = -1;
         int beginBitInInst = -1, endBitInInst = -1;
@@ -197,20 +197,20 @@ void CodeEmitterGen::run(std::ostream &o) {
         // this is not an operand!!
         if (beginBitInInst != -1) {
           o << "      // op" << op << ": " << Vals[i].getName() << "\n"
-            << "      int64_t op" << op 
+            << "      int64_t op" << op
             <<" = getMachineOpValue(MI, MI.getOperand("<<op<<"));\n";
           //<< "   MachineOperand &op" << op <<" = MI.getOperand("<<op<<");\n";
           OpOrder[Vals[i].getName()] = op++;
-          
-          DEBUG(o << "      // Var: begin = " << beginBitInVar 
+
+          DEBUG(o << "      // Var: begin = " << beginBitInVar
                   << ", end = " << endBitInVar
                   << "; Inst: begin = " << beginBitInInst
                   << ", end = " << endBitInInst << "\n");
-          
+
           if (continuous) {
             DEBUG(o << "      // continuous: op" << OpOrder[Vals[i].getName()]
                     << "\n");
-            
+
             // Mask off the right bits
             // Low mask (ie. shift, if necessary)
             assert(endBitInVar >= 0 && "Negative shift amount in masking!");
@@ -220,21 +220,21 @@ void CodeEmitterGen::run(std::ostream &o) {
               beginBitInVar -= endBitInVar;
               endBitInVar = 0;
             }
-            
+
             // High mask
             o << "      op" << OpOrder[Vals[i].getName()]
               << " &= (1<<" << beginBitInVar+1 << ") - 1;\n";
-            
+
             // Shift the value to the correct place (according to place in inst)
             assert(endBitInInst >= 0 && "Negative shift amount!");
             if (endBitInInst != 0)
               o << "      op" << OpOrder[Vals[i].getName()]
               << " <<= " << endBitInInst << ";\n";
-            
+
             // Just OR in the result
             o << "      Value |= op" << OpOrder[Vals[i].getName()] << ";\n";
           }
-          
+
           // otherwise, will be taken care of in the loop below using this
           // value:
           OpContinuous[Vals[i].getName()] = continuous;
diff --git a/utils/TableGen/CodeEmitterGen.h b/utils/TableGen/CodeEmitterGen.h
index 5bb220dd4a..6089f70e99 100644
--- a/utils/TableGen/CodeEmitterGen.h
+++ b/utils/TableGen/CodeEmitterGen.h
@@ -1,10 +1,10 @@
 //===- CodeEmitterGen.h - Code Emitter Generator ----------------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // FIXME: document
@@ -26,7 +26,7 @@ class CodeEmitterGen : public TableGenBackend {
   RecordKeeper &Records;
 public:
   CodeEmitterGen(RecordKeeper &R) : Records(R) {}
-  
+
   // run - Output the code emitter
   void run(std::ostream &o);
 private:
diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h
index 62b0289ed6..3b3babf592 100644
--- a/utils/TableGen/CodeGenInstruction.h
+++ b/utils/TableGen/CodeGenInstruction.h
@@ -1,10 +1,10 @@
 //===- CodeGenInstruction.h - Instruction Class Wrapper ---------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines a wrapper class for the 'Instruction' TableGen class.
@@ -61,7 +61,7 @@ namespace llvm {
                   const std::string &PMN, unsigned MION)
         : Rec(R), Ty(T), Name(N), PrinterMethodName(PMN), MIOperandNo(MION) {}
     };
-    
+
     /// OperandList - The list of declared operands, along with their declared
     /// type (which is a record).
     std::vector<OperandInfo> OperandList;
diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h
index e6838d5729..2cd312941b 100644
--- a/utils/TableGen/CodeGenRegisters.h
+++ b/utils/TableGen/CodeGenRegisters.h
@@ -1,10 +1,10 @@
 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines structures to encapsulate information gleaned from the
diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index cb241aaf95..02678e9821 100644
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -1,10 +1,10 @@
 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper ---------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This class wrap target description classes used by the various code
@@ -77,7 +77,7 @@ std::ostream &llvm::operator<<(std::ostream &OS, MVT::ValueType T) {
 CodeGenTarget::CodeGenTarget() : PointerType(MVT::Other) {
   std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
   if (Targets.size() == 0)
-    throw std::string("ERROR: No 'Target' subclasses defined!");  
+    throw std::string("ERROR: No 'Target' subclasses defined!");
   if (Targets.size() != 1)
     throw std::string("ERROR: Multiple subclasses of Target defined!");
   TargetRec = Targets[0];
@@ -155,7 +155,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
   ListInit *RegList = R->getValueAsListInit("MemberList");
   for (unsigned i = 0, e = RegList->getSize(); i != e; ++i) {
     DefInit *RegDef = dynamic_cast<DefInit*>(RegList->getElement(i));
-    if (!RegDef) throw "Register class member is not a record!";      
+    if (!RegDef) throw "Register class member is not a record!";
     Record *Reg = RegDef->getDef();
 
     if (!Reg->isSubClassOf("Register"))
@@ -257,7 +257,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
         } else
           throw "Unknown operand class '" + Rec->getName() +
                 "' in instruction '" + R->getName() + "' instruction!";
-        
+
         OperandList.push_back(OperandInfo(Rec, Ty, DI->getArgName(i),
                                           PrintMethod, MIOperandNo));
         MIOperandNo += NumOps;
diff --git a/utils/TableGen/CodeGenTarget.h b/utils/TableGen/CodeGenTarget.h
index 2d89915447..05d5cb2ddb 100644
--- a/utils/TableGen/CodeGenTarget.h
+++ b/utils/TableGen/CodeGenTarget.h
@@ -1,10 +1,10 @@
 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines wrappers for the Target class and related global
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index bde5fdc959..64629b4863 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -1,10 +1,10 @@
 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend is responsible for emitting a description of the target
@@ -135,13 +135,13 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   LI = Inst.TheDef->getValueAsListInit("Uses");
   if (!LI->getSize())
     OS << "EmptyImpUses, ";
-  else 
+  else
     OS << Inst.TheDef->getName() << "ImpUses, ";
 
   LI = Inst.TheDef->getValueAsListInit("Defs");
   if (!LI->getSize())
     OS << "EmptyImpDefs ";
-  else 
+  else
     OS << Inst.TheDef->getName() << "ImpDefs ";
 
   OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
diff --git a/utils/TableGen/InstrInfoEmitter.h b/utils/TableGen/InstrInfoEmitter.h
index bf7da347ed..005fd3810b 100644
--- a/utils/TableGen/InstrInfoEmitter.h
+++ b/utils/TableGen/InstrInfoEmitter.h
@@ -1,10 +1,10 @@
 //===- InstrInfoEmitter.h - Generate a Instruction Set Desc. ----*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend is responsible for emitting a description of the target
@@ -28,7 +28,7 @@ class InstrInfoEmitter : public TableGenBackend {
   RecordKeeper &Records;
 public:
   InstrInfoEmitter(RecordKeeper &R) : Records(R) {}
-  
+
   // run - Output the instruction set description, returning true on failure.
   void run(std::ostream &OS);
 
diff --git a/utils/TableGen/InstrSelectorEmitter.cpp b/utils/TableGen/InstrSelectorEmitter.cpp
index e9c63441ae..4105199c91 100644
--- a/utils/TableGen/InstrSelectorEmitter.cpp
+++ b/utils/TableGen/InstrSelectorEmitter.cpp
@@ -1,10 +1,10 @@
 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend is responsible for emitting a description of the target
@@ -69,7 +69,7 @@ void TreePatternNode::InstantiateNonterminals(InstrSelectorEmitter &ISE) {
       getChild(i)->InstantiateNonterminals(ISE);
     return;
   }
-  
+
   // If this is a leaf, it might be a reference to a nonterminal!  Check now.
   Record *R = getValueRecord();
   if (R->isSubClassOf("Nonterminal")) {
@@ -78,7 +78,7 @@ void TreePatternNode::InstantiateNonterminals(InstrSelectorEmitter &ISE) {
       // We found an unresolved nonterminal reference.  Ask the ISE to clone
       // it for us, then update our reference to the fresh, new, resolved,
       // nonterminal.
-      
+
       Value = new DefInit(ISE.InstantiateNonterminal(NT, getType()));
     }
   }
@@ -107,12 +107,12 @@ std::ostream &llvm::operator<<(std::ostream &OS, const TreePatternNode &N) {
     return OS << N.getType() << ":" << *N.getValue();
   OS << "(" << N.getType() << ":";
   OS << N.getOperator()->getName();
-  
+
   if (N.getNumChildren() != 0) {
     OS << " " << *N.getChild(0);
     for (unsigned i = 1, e = N.getNumChildren(); i != e; ++i)
       OS << ", " << *N.getChild(i);
-  }  
+  }
   return OS << ")";
 }
 
@@ -162,7 +162,7 @@ void Pattern::error(const std::string &Msg) const {
   case Instruction: M += "instruction "; break;
   case Expander   : M += "expander "; break;
   }
-  throw M + TheRecord->getName() + ": " + Msg;  
+  throw M + TheRecord->getName() + ": " + Msg;
 }
 
 /// calculateArgs - Compute the list of all of the arguments to this pattern,
@@ -205,7 +205,7 @@ TreePatternNode *Pattern::ParseTreePattern(DagInit *Dag) {
     // node.
     if (Dag->getNumArgs() != 1)
       error("Type cast only valid for a leaf node!");
-    
+
     Init *Arg = Dag->getArg(0);
     TreePatternNode *New;
     if (DefInit *DI = dynamic_cast<DefInit*>(Arg)) {
@@ -229,7 +229,7 @@ TreePatternNode *Pattern::ParseTreePattern(DagInit *Dag) {
     error("Unrecognized node '" + Operator->getName() + "'!");
 
   std::vector<std::pair<TreePatternNode*, std::string> > Children;
-  
+
   for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
     Init *Arg = Dag->getArg(i);
     if (DagInit *DI = dynamic_cast<DagInit*>(Arg)) {
@@ -442,7 +442,7 @@ void InstrSelectorEmitter::ReadNodeTypes() {
   DEBUG(std::cerr << "Getting node types: ");
   for (unsigned i = 0, e = Nodes.size(); i != e; ++i) {
     Record *Node = Nodes[i];
-    
+
     // Translate the return type...
     NodeType::ArgResultTypes RetTy =
       NodeType::Translate(Node->getValueAsDef("RetType"));
@@ -545,7 +545,7 @@ Record *InstrSelectorEmitter::InstantiateNonterminal(Pattern *NT,
   // Check to see if we have already instantiated this pair...
   Record* &Slot = InstantiatedNTs[std::make_pair(NT, ResultTy)];
   if (Slot) return Slot;
-  
+
   Record *New = new Record(NT->getRecord()->getName()+"_"+getName(ResultTy));
 
   // Copy over the superclasses...
@@ -685,7 +685,7 @@ void InstrSelectorEmitter::EmitMatchCosters(std::ostream &OS,
                                             unsigned IndentAmt) {
   assert(!Patterns.empty() && "No patterns to emit matchers for!");
   std::string Indent(IndentAmt, ' ');
-  
+
   // Load all of the operands of the root node into scalars for fast access
   const NodeType &ONT = getNodeType(Patterns[0].second->getOperator());
   for (unsigned i = 0, e = ONT.ArgTypes.size(); i != e; ++i)
@@ -719,7 +719,7 @@ void InstrSelectorEmitter::EmitMatchCosters(std::ostream &OS,
   std::string LocCostName = VarPrefix + "_Cost";
   OS << Indent << "unsigned " << LocCostName << "Min = ~0U >> 1;\n"
      << Indent << "unsigned " << VarPrefix << "_PatternMin = NoMatchPattern;\n";
-  
+
 #if 0
   // Separate out all of the patterns into groups based on what their top-level
   // signature looks like...
@@ -789,7 +789,7 @@ void InstrSelectorEmitter::EmitMatchCosters(std::ostream &OS,
     OS << Indent << "  if (" << LocCostName << " < " << LocCostName << "Min) { "
        << LocCostName << "Min = " << LocCostName << "; " << VarPrefix
        << "_PatternMin = " << VarPrefix << "_Pattern; }\n";
-    
+
     OS << Indent << "}\n";
   }
 #endif
@@ -938,7 +938,7 @@ void InstrSelectorEmitter::PrintExpanderOperand(Init *Arg,
   P->error("Unknown operand type to expander!");
 }
 
-static std::string getArgName(Pattern *P, const std::string &ArgName, 
+static std::string getArgName(Pattern *P, const std::string &ArgName,
        const std::vector<std::pair<TreePatternNode*, std::string> > &Operands) {
   assert(P->getNumArgs() == Operands.size() &&"Argument computation mismatch!");
   if (ArgName.empty()) return "";
@@ -957,7 +957,7 @@ static std::string getArgName(Pattern *P, const std::string &ArgName,
 void InstrSelectorEmitter::run(std::ostream &OS) {
   // Type-check all of the node types to ensure we "understand" them.
   ReadNodeTypes();
-  
+
   // Read in all of the nonterminals, instructions, and expanders...
   ReadNonterminals();
   ReadInstructionPatterns();
@@ -977,7 +977,7 @@ void InstrSelectorEmitter::run(std::ostream &OS) {
       DEBUG(std::cerr << "  " << *I->second << "\n");
 
   CalculateComputableValues();
-  
+
   OS << "#include \"llvm/CodeGen/MachineInstrBuilder.h\"\n";
 
   EmitSourceFileHeader("Instruction Selector for the " + Target.getName() +
@@ -1127,13 +1127,13 @@ void InstrSelectorEmitter::run(std::ostream &OS) {
         OS << getNodeName(Operator) << "(SelectionDAGNode *N) {\n"
            << "  unsigned Pattern = NoMatchPattern;\n"
            << "  unsigned MinCost = ~0U >> 1;\n";
-        
+
         std::vector<std::pair<Pattern*, TreePatternNode*> > Patterns;
         for (unsigned i = 0, e = J->second.size(); i != e; ++i)
           Patterns.push_back(std::make_pair(J->second[i],
                                             J->second[i]->getTree()));
         EmitMatchCosters(OS, Patterns, "N", 2);
-        
+
         OS << "\n  N->setPatternCostFor(" << SlotName
            << "_Slot, Pattern, MinCost, NumSlots);\n"
            << "  return MinCost;\n"
@@ -1172,7 +1172,7 @@ void InstrSelectorEmitter::run(std::ostream &OS) {
         // Loop over the operands, reducing them...
         std::vector<std::pair<TreePatternNode*, std::string> > Operands;
         ReduceAllOperands(P->getTree(), "N", Operands, OS);
-        
+
         // Now that we have reduced all of our operands, and have the values
         // that reduction produces, perform the reduction action for this
         // pattern.
@@ -1206,7 +1206,7 @@ void InstrSelectorEmitter::run(std::ostream &OS) {
                      << "->Val";
                 });
         DEBUG(OS << " << \"\\n\";\n");
-        
+
         // Generate the reduction code appropriate to the particular type of
         // pattern that this is...
         switch (P->getPatternType()) {
@@ -1245,7 +1245,7 @@ void InstrSelectorEmitter::run(std::ostream &OS) {
             Pattern *InstPat = getPattern(InstRec);
             if (!InstPat || InstPat->getPatternType() != Pattern::Instruction)
               P->error("Instruction list must contain Instruction patterns!");
-            
+
             bool hasResult = InstPat->getResult() != 0;
             if (InstPat->getNumArgs() != DIInst->getNumArgs()-hasResult) {
               P->error("Incorrect number of arguments specified for inst '" +
@@ -1286,8 +1286,8 @@ void InstrSelectorEmitter::run(std::ostream &OS) {
            << "    break;\n"
            << "  }\n";
       }
-    
-    
+
+
     OS << "  default: assert(0 && \"Unknown " << SlotName << " pattern!\");\n"
        << "  }\n\n  N->addValue(Val);  // Do not ever recalculate this\n"
        << "  return Val;\n}\n\n";
diff --git a/utils/TableGen/InstrSelectorEmitter.h b/utils/TableGen/InstrSelectorEmitter.h
index 302a98adc3..fbf31f2629 100644
--- a/utils/TableGen/InstrSelectorEmitter.h
+++ b/utils/TableGen/InstrSelectorEmitter.h
@@ -1,10 +1,10 @@
 //===- InstrInfoEmitter.h - Generate a Instruction Set Desc. ----*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend is responsible for emitting a description of the target
@@ -147,7 +147,7 @@ private:
   /// there was a (set) node on the outside level that it has been stripped off.
   ///
   TreePatternNode *Tree;
-  
+
   /// Result - If this is an instruction or expander pattern, this is the
   /// register result, specified with a (set) in the pattern.
   ///
@@ -195,7 +195,7 @@ public:
   /// getTree - Return the tree pattern which corresponds to this pattern.
   ///
   TreePatternNode *getTree() const { return Tree; }
-  
+
   Record *getResult() const {
     return ResultNode ? ResultNode->getValueRecord() : 0;
   }
@@ -319,7 +319,7 @@ class InstrSelectorEmitter : public TableGenBackend {
 
 public:
   InstrSelectorEmitter(RecordKeeper &R) : Records(R) {}
-  
+
   // run - Output the instruction set description, returning true on failure.
   void run(std::ostream &OS);
 
@@ -369,7 +369,7 @@ private:
   // InstantiateNonterminals - Instantiate any unresolved nonterminals with
   // information from the context that they are used in.
   void InstantiateNonterminals();
-  
+
   // CalculateComputableValues - Fill in the ComputableValues map through
   // analysis of the patterns we are playing with.
   void CalculateComputableValues();
@@ -381,7 +381,7 @@ private:
   void EmitMatchCosters(std::ostream &OS,
             const std::vector<std::pair<Pattern*, TreePatternNode*> > &Patterns,
                         const std::string &VarPrefix, unsigned Indent);
-  
+
   /// PrintExpanderOperand - Print out Arg as part of the instruction emission
   /// process for the expander pattern P.  This argument may be referencing some
   /// values defined in P, or may just be physical register references or
diff --git a/utils/TableGen/Record.cpp b/utils/TableGen/Record.cpp
index 9c2d381de6..c6bf403617 100644
--- a/utils/TableGen/Record.cpp
+++ b/utils/TableGen/Record.cpp
@@ -1,10 +1,10 @@
 //===- Record.cpp - Record implementation ---------------------------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 //
@@ -32,8 +32,8 @@ bool BitRecTy::baseClassOf(const BitsRecTy *RHS) const {
 Init *BitRecTy::convertValue(IntInit *II) {
   int Val = II->getValue();
   if (Val != 0 && Val != 1) return 0;  // Only accept 0 or 1 for a bit!
-  
-  return new BitInit(Val != 0); 
+
+  return new BitInit(Val != 0);
 }
 
 Init *BitRecTy::convertValue(TypedInit *VI) {
@@ -98,7 +98,7 @@ Init *BitsRecTy::convertValue(TypedInit *VI) {
     Ret->setBit(0, VI);
     return Ret;
   }
-      
+
   return 0;
 }
 
@@ -108,7 +108,7 @@ Init *IntRecTy::convertValue(BitInit *BI) {
 
 Init *IntRecTy::convertValue(BitsInit *BI) {
   int Result = 0;
-  for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) 
+  for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i)
     if (BitInit *Bit = dynamic_cast<BitInit*>(BI->getBit(i))) {
       Result |= Bit->getValue() << i;
     } else {
@@ -230,7 +230,7 @@ void BitsInit::print(std::ostream &OS) const {
 bool BitsInit::printInHex(std::ostream &OS) const {
   // First, attempt to convert the value into an integer value...
   int Result = 0;
-  for (unsigned i = 0, e = getNumBits(); i != e; ++i) 
+  for (unsigned i = 0, e = getNumBits(); i != e; ++i)
     if (BitInit *Bit = dynamic_cast<BitInit*>(getBit(i))) {
       Result |= Bit->getValue() << i;
     } else {
@@ -265,7 +265,7 @@ bool BitsInit::printAsVariable(std::ostream &OS) const {
 }
 
 bool BitsInit::printAsUnset(std::ostream &OS) const {
-  for (unsigned i = 0, e = getNumBits(); i != e; ++i) 
+  for (unsigned i = 0, e = getNumBits(); i != e; ++i)
     if (!dynamic_cast<UnsetInit*>(getBit(i)))
       return true;
   OS << "?";
@@ -406,7 +406,7 @@ Init *VarInit::resolveBitReference(Record &R, const RecordVal *IRV,
   assert(RV && "Reference to a non-existant variable?");
   assert(dynamic_cast<BitsInit*>(RV->getValue()));
   BitsInit *BI = (BitsInit*)RV->getValue();
-  
+
   assert(Bit < BI->getNumBits() && "Bit reference out of range!");
   Init *B = BI->getBit(Bit);
 
@@ -465,7 +465,7 @@ Init *VarInit::resolveReferences(Record &R, const RecordVal *RV) {
       return Val->getValue();
   return this;
 }
-  
+
 
 Init *VarBitInit::resolveReferences(Record &R, const RecordVal *RV) {
   if (Init *I = getVariable()->resolveBitReference(R, RV, getBitNum()))
@@ -515,7 +515,7 @@ Init *FieldInit::resolveBitReference(Record &R, const RecordVal *RV,
     if (BitsInit *BI = dynamic_cast<BitsInit*>(BitsVal)) {
       assert(Bit < BI->getNumBits() && "Bit reference out of range!");
       Init *B = BI->getBit(Bit);
-      
+
       if (dynamic_cast<BitInit*>(B))  // If the bit is set...
         return B;                     // Replace the VarBitInit with it.
     }
@@ -770,7 +770,7 @@ std::ostream &llvm::operator<<(std::ostream &OS, const RecordKeeper &RK) {
   for (std::map<std::string, Record*>::const_iterator I = Classes.begin(),
 	 E = Classes.end(); I != E; ++I)
     OS << "class " << *I->second;
-  
+
   OS << "------------- Defs -----------------\n";
   const std::map<std::string, Record*> &Defs = RK.getDefs();
   for (std::map<std::string, Record*>::const_iterator I = Defs.begin(),
diff --git a/utils/TableGen/Record.h b/utils/TableGen/Record.h
index 59274535e9..c5bdf3a402 100644
--- a/utils/TableGen/Record.h
+++ b/utils/TableGen/Record.h
@@ -1,10 +1,10 @@
 //===- Record.h - Classes to represent Table Records ------------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines the main TableGen data structures, including the TableGen
@@ -280,7 +280,7 @@ public:
   virtual Init *convertValue( TypedInit *TI);
   virtual Init *convertValue(   VarInit *VI) { return RecTy::convertValue(VI);}
   virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(FI);}
-  
+
   void print(std::ostream &OS) const;
 
   bool typeIsConvertibleTo(const RecTy *RHS) const {
@@ -292,7 +292,7 @@ public:
   virtual bool baseClassOf(const IntRecTy    *RHS) const { return false; }
   virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
   virtual bool baseClassOf(const ListRecTy   *RHS) const {
-    return RHS->getElementType()->typeIsConvertibleTo(Ty); 
+    return RHS->getElementType()->typeIsConvertibleTo(Ty);
   }
   virtual bool baseClassOf(const CodeRecTy   *RHS) const { return false; }
   virtual bool baseClassOf(const DagRecTy    *RHS) const { return false; }
@@ -388,7 +388,7 @@ public:
   virtual Init *convertValue(VarBitInit *VB) { return 0; }
   virtual Init *convertValue(   DefInit *DI);
   virtual Init *convertValue(   DagInit *DI) { return 0; }
-  virtual Init *convertValue( TypedInit *VI); 
+  virtual Init *convertValue( TypedInit *VI);
   virtual Init *convertValue(   VarInit *VI) { return RecTy::convertValue(VI);}
   virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(FI);}
 
@@ -464,7 +464,7 @@ struct Init {
   virtual Init *getFieldInit(Record &R, const std::string &FieldName) const {
     return 0;
   }
-  
+
   enum BinaryOp { SHL, SRA, SRL };
   virtual Init *getBinaryOp(BinaryOp Op, Init *RHS) {
     return 0;
@@ -645,7 +645,7 @@ public:
 ///
 class TypedInit : public Init {
   RecTy *Ty;
-public:  
+public:
   TypedInit(RecTy *T) : Ty(T) {}
 
   RecTy *getType() const { return Ty; }
@@ -673,7 +673,7 @@ class VarInit : public TypedInit {
   std::string VarName;
 public:
   VarInit(const std::string &VN, RecTy *T) : TypedInit(T), VarName(VN) {}
-  
+
   virtual Init *convertInitializerTo(RecTy *Ty) {
     return Ty->convertValue(this);
   }
@@ -694,7 +694,7 @@ public:
   /// users of the value to allow the value to propagate out.
   ///
   virtual Init *resolveReferences(Record &R, const RecordVal *RV);
-  
+
   virtual void print(std::ostream &OS) const { OS << VarName; }
 };
 
@@ -717,14 +717,14 @@ public:
 
   TypedInit *getVariable() const { return TI; }
   unsigned getBitNum() const { return Bit; }
-  
+
   virtual void print(std::ostream &OS) const {
     TI->print(OS); OS << "{" << Bit << "}";
   }
   virtual Init *resolveReferences(Record &R, const RecordVal *RV);
 };
 
-/// VarListElementInit - List[4] - Represent access to one element of a var or 
+/// VarListElementInit - List[4] - Represent access to one element of a var or
 /// field.
 class VarListElementInit : public TypedInit {
   TypedInit *TI;
@@ -765,7 +765,7 @@ class DefInit : public Init {
   Record *Def;
 public:
   DefInit(Record *D) : Def(D) {}
-  
+
   virtual Init *convertInitializerTo(RecTy *Ty) {
     return Ty->convertValue(this);
   }
@@ -776,7 +776,7 @@ public:
 
   virtual RecTy *getFieldType(const std::string &FieldName) const;
   virtual Init *getFieldInit(Record &R, const std::string &FieldName) const;
-  
+
   virtual void print(std::ostream &OS) const;
 };
 
@@ -826,7 +826,7 @@ public:
       ArgNames.push_back(args[i].second);
     }
   }
-  
+
   virtual Init *convertInitializerTo(RecTy *Ty) {
     return Ty->convertValue(this);
   }
@@ -1037,7 +1037,7 @@ public:
 	   E = Defs.end(); I != E; ++I)
       delete I->second;
   }
-  
+
   const std::map<std::string, Record*> &getClasses() const { return Classes; }
   const std::map<std::string, Record*> &getDefs() const { return Defs; }
 
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index e37442b1c9..5fda93f8d1 100644
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1,10 +1,10 @@
 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend is responsible for emitting a description of a target
@@ -38,7 +38,7 @@ void RegisterInfoEmitter::runEnums(std::ostream &OS) {
 
   for (unsigned i = 0, e = Registers.size(); i != e; ++i)
     OS << "    " << Registers[i].getName() << ", \t// " << i+1 << "\n";
-  
+
   OS << "  };\n";
   if (!Namespace.empty())
     OS << "}\n";
@@ -162,11 +162,11 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
                   << " specified multiple times!\n";
       RegisterAliases[Reg->getDef()].insert(R);
     }
-  } 
+  }
 
   if (!RegisterAliases.empty())
     OS << "\n\n  // Register Alias Sets...\n";
-  
+
   // Emit the empty alias list
   OS << "  const unsigned Empty_AliasSet[] = { 0 };\n";
   // Loop over all of the registers which have aliases, emitting the alias list
@@ -223,7 +223,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
               Reg.getName() + "'!";
     }
 
-    OS << SpillSize << ", " << SpillAlign << " },\n";    
+    OS << SpillSize << ", " << SpillAlign << " },\n";
   }
   OS << "  };\n";      // End of register descriptors...
   OS << "}\n\n";       // End of anonymous namespace...
@@ -240,21 +240,21 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
 
 
   std::string ClassName = Target.getName() + "GenRegisterInfo";
-  
+
   // Emit the constructor of the class...
   OS << ClassName << "::" << ClassName
      << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
      << "  : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1
      << ", RegisterClasses, RegisterClasses+" << RegClassNames.size() << ",\n "
      << "                 CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
-  
+
   // Emit the getCalleeSaveRegs method...
   OS << "const unsigned* " << ClassName << "::getCalleeSaveRegs() const {\n"
      << "  static const unsigned CalleeSaveRegs[] = {\n    ";
 
   const std::vector<Record*> &CSR = Target.getCalleeSavedRegisters();
   for (unsigned i = 0, e = CSR.size(); i != e; ++i)
-    OS << getQualifiedName(CSR[i]) << ", ";  
+    OS << getQualifiedName(CSR[i]) << ", ";
   OS << " 0\n  };\n  return CalleeSaveRegs;\n}\n\n";
   OS << "} // End llvm namespace \n";
 }
diff --git a/utils/TableGen/RegisterInfoEmitter.h b/utils/TableGen/RegisterInfoEmitter.h
index 1e6380b70a..06e2e5cf5a 100644
--- a/utils/TableGen/RegisterInfoEmitter.h
+++ b/utils/TableGen/RegisterInfoEmitter.h
@@ -1,10 +1,10 @@
 //===- RegisterInfoEmitter.h - Generate a Register File Desc. ---*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend is responsible for emitting a description of a target
@@ -24,7 +24,7 @@ class RegisterInfoEmitter : public TableGenBackend {
   RecordKeeper &Records;
 public:
   RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
-  
+
   // run - Output the register file description, returning true on failure.
   void run(std::ostream &o);
 
diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index ecce8e0f20..9f1ded1299 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -1,10 +1,10 @@
 //===- TableGen.cpp - Top-Level TableGen implementation -------------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // TableGen is a tool which can be used to build up a description of something,
@@ -158,7 +158,7 @@ static void FindInstDifferences(Record *I1, Record *I2,
   unsigned LastFixedBit = FirstVaryingBit;
   while (LastFixedBit < MaxBits && BitsAreFixed(I1, I2, LastFixedBit))
     ++LastFixedBit;
-  
+
   if (FirstVaryingBit < FirstVaryingBitOverall)
     FirstVaryingBitOverall = FirstVaryingBit;
   if (LastFixedBit < LastFixedBitOverall)
@@ -187,7 +187,7 @@ struct BitComparator {
   }
 };
 
-static void PrintRange(std::vector<Record*>::iterator I, 
+static void PrintRange(std::vector<Record*>::iterator I,
 		       std::vector<Record*>::iterator E) {
   while (I != E) std::cerr << **I++;
 }
@@ -210,7 +210,7 @@ static unsigned getFirstFixedBitInSequence(std::vector<Record*>::iterator IB,
 // instructions that we may have found.  Eventually, this list will get pared
 // down to zero or one instruction, in which case we have a match or failure.
 //
-static Record *ParseMachineCode(std::vector<Record*>::iterator InstsB, 
+static Record *ParseMachineCode(std::vector<Record*>::iterator InstsB,
 				std::vector<Record*>::iterator InstsE,
 				unsigned char *M) {
   assert(InstsB != InstsE && "Empty range?");
@@ -269,7 +269,7 @@ static Record *ParseMachineCode(std::vector<Record*>::iterator InstsB,
     while (RangeEnd != InstsE &&
           BitRangesEqual(*RangeBegin, *RangeEnd, FirstVaryingBit, LastFixedBit))
       ++RangeEnd;
-    
+
     // We just identified a range of equal instructions.  If this range is the
     // input range, we were not able to distinguish between the instructions in
     // the set.  Print an error and exit!
@@ -279,7 +279,7 @@ static Record *ParseMachineCode(std::vector<Record*>::iterator InstsB,
       PrintRange(InstsB, InstsE);
       exit(1);
     }
-    
+
 #if 0
     std::cerr << "FVB: " << FirstVaryingBit << " - " << LastFixedBit
 	      << ": [" << RangeEnd-RangeBegin << "] - ";
@@ -316,7 +316,7 @@ static void PrintValue(Record *I, unsigned char *Ptr, const RecordVal &Val) {
   for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i)
     if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(i)))
       Value |= B->getValue() << i;
-  
+
   // Loop over all of the fields in the instruction adding in any
   // contributions to this value (due to bit references).
   //
@@ -330,7 +330,7 @@ static void PrintValue(Record *I, unsigned char *Ptr, const RecordVal &Val) {
 	  Value |= getMemoryBit(Ptr, Offset+i) << i;
 	break;
       }
-      
+
       // Scan through the field looking for bit initializers of the current
       // variable...
       for (unsigned i = 0, e = FieldInitializer->getNumBits(); i != e; ++i)
@@ -355,7 +355,7 @@ static void PrintInstruction(Record *I, unsigned char *Ptr) {
   std::cout << "Inst " << getNumBits(I)/8 << " bytes: "
 	    << "\t" << I->getName() << "\t" << *I->getValue("Name")->getValue()
 	    << "\t";
-  
+
   const std::vector<RecordVal> &Vals = I->getValues();
   for (unsigned i = 0, e = Vals.size(); i != e; ++i)
     if (!Vals[i].getValue()->isComplete()) {
@@ -363,7 +363,7 @@ static void PrintInstruction(Record *I, unsigned char *Ptr) {
       PrintValue(I, Ptr, Vals[i]);
       std::cout << "\t";
     }
-  
+
   std::cout << "\n";// << *I;
 }
 
@@ -390,7 +390,7 @@ static void ParseMachineCode() {
 
 #if 0
   // SparcV9 code
-  unsigned char Buffer[] = { 0xbf, 0xe0, 0x20, 0x1f, 0x1, 0x0, 0x0, 0x1, 
+  unsigned char Buffer[] = { 0xbf, 0xe0, 0x20, 0x1f, 0x1, 0x0, 0x0, 0x1,
                              0x0, 0x0, 0x0, 0x0, 0xc1, 0x0, 0x20, 0x1, 0x1,
                              0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
                              0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x1,
diff --git a/utils/TableGen/TableGenBackend.cpp b/utils/TableGen/TableGenBackend.cpp
index 3e418f6ce6..716bb4886c 100644
--- a/utils/TableGen/TableGenBackend.cpp
+++ b/utils/TableGen/TableGenBackend.cpp
@@ -1,10 +1,10 @@
 //===- TableGenBackend.cpp - Base class for TableGen Backends ---*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file provides useful services for TableGen backends...
diff --git a/utils/TableGen/TableGenBackend.h b/utils/TableGen/TableGenBackend.h
index deeb385f69..9e9089e22f 100644
--- a/utils/TableGen/TableGenBackend.h
+++ b/utils/TableGen/TableGenBackend.h
@@ -1,10 +1,10 @@
 //===- TableGenBackend.h - Base class for TableGen Backends -----*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // The TableGenBackend class is provided as a common interface for all TableGen
diff --git a/utils/fpcmp/fpcmp.cpp b/utils/fpcmp/fpcmp.cpp
index cdaf95de61..913fde50e5 100644
--- a/utils/fpcmp/fpcmp.cpp
+++ b/utils/fpcmp/fpcmp.cpp
@@ -1,10 +1,10 @@
 //===- fpcmp.cpp - A fuzzy "cmp" that permits floating point noise --------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // fpcmp is a tool that basically works like the 'cmp' tool, except that it can