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author | Chris Lattner <sabre@nondot.org> | 2009-08-08 01:32:19 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2009-08-08 01:32:19 +0000 |
commit | 41aefdcdd1c1631041834d53ffada106a5cfaf02 (patch) | |
tree | a86d88b076b567a06fcdade74b1d0f9ae887effc /utils | |
parent | 8a1871d10b3c8cdbac9b8378eebd95461790d1e6 (diff) | |
download | llvm-41aefdcdd1c1631041834d53ffada106a5cfaf02.tar.gz llvm-41aefdcdd1c1631041834d53ffada106a5cfaf02.tar.bz2 llvm-41aefdcdd1c1631041834d53ffada106a5cfaf02.tar.xz |
make printInstruction return void since its result is omitted. Make the
error condition get trapped with an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78449 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r-- | utils/TableGen/AsmWriterEmitter.cpp | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index 95d4aac130..61117c16a3 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -451,7 +451,7 @@ FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands, // If this is the last operand, emit a return. if (Inst->Operands.size() == 1) - Command += " return true;\n"; + Command += " return;\n"; // Check to see if we already have 'Command' in UniqueOperandCommands. // If not, add it. @@ -529,7 +529,7 @@ FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands, // Don't early-out too soon. Other instructions in this // group may have more operands. FirstInst->Operands.size() == MaxSize) { - Command += " return true;\n"; + Command += " return;\n"; } UniqueOperandCommands[CommandIdx] += Command; @@ -565,7 +565,7 @@ void AsmWriterEmitter::run(raw_ostream &O) { "/// from the instruction set description. This method returns true if the\n" "/// machine instruction was sufficiently described to print it, otherwise\n" "/// it returns false.\n" - "bool " << Target.getName() << ClassName + "void " << Target.getName() << ClassName << "::printInstruction(const MachineInstr *MI) {\n"; std::vector<AsmWriterInst> Instructions; @@ -640,7 +640,7 @@ void AsmWriterEmitter::run(raw_ostream &O) { // For the first operand check, add a default value for instructions with // just opcode strings to use. if (isFirst) { - UniqueOperandCommands.push_back(" return true;\n"); + UniqueOperandCommands.push_back(" return;\n"); isFirst = false; } @@ -733,16 +733,16 @@ void AsmWriterEmitter::run(raw_ostream &O) { O << " if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {\n" << " O << \"\\t\";\n" << " printInlineAsm(MI);\n" - << " return true;\n" + << " return;\n" << " } else if (MI->isLabel()) {\n" << " printLabel(MI);\n" - << " return true;\n" + << " return;\n" << " } else if (MI->getOpcode() == TargetInstrInfo::DECLARE) {\n" << " printDeclare(MI);\n" - << " return true;\n" + << " return;\n" << " } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {\n" << " printImplicitDef(MI);\n" - << " return true;\n" + << " return;\n" << " }\n\n"; O << "\n#endif\n"; @@ -751,7 +751,7 @@ void AsmWriterEmitter::run(raw_ostream &O) { O << " // Emit the opcode for the instruction.\n" << " unsigned Bits = OpInfo[MI->getOpcode()];\n" - << " if (Bits == 0) return false;\n" + << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ");\n\n"; // Output the table driven operand information. @@ -815,9 +815,9 @@ void AsmWriterEmitter::run(raw_ostream &O) { EmitInstructions(Instructions, O); O << " }\n"; - O << " return true;\n"; + O << " return;\n"; } - O << " return true;\n"; + O << " return;\n"; O << "}\n"; } |