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author | Craig Topper <craig.topper@gmail.com> | 2011-09-23 06:57:25 +0000 |
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committer | Craig Topper <craig.topper@gmail.com> | 2011-09-23 06:57:25 +0000 |
commit | 4da632e6e09b96db4b3f9202cde4e6ca732001c1 (patch) | |
tree | 2b2c73074cefca6d6e072e2615db00e10753fd93 /utils | |
parent | aaa9fc2e375ac92c9ff0cff5265c79045affe8ba (diff) | |
download | llvm-4da632e6e09b96db4b3f9202cde4e6ca732001c1.tar.gz llvm-4da632e6e09b96db4b3f9202cde4e6ca732001c1.tar.bz2 llvm-4da632e6e09b96db4b3f9202cde4e6ca732001c1.tar.xz |
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r-- | utils/TableGen/X86DisassemblerTables.cpp | 6 | ||||
-rw-r--r-- | utils/TableGen/X86DisassemblerTables.h | 4 | ||||
-rw-r--r-- | utils/TableGen/X86RecognizableInstr.cpp | 11 | ||||
-rw-r--r-- | utils/TableGen/X86RecognizableInstr.h | 4 |
4 files changed, 19 insertions, 6 deletions
diff --git a/utils/TableGen/X86DisassemblerTables.cpp b/utils/TableGen/X86DisassemblerTables.cpp index aed27279a5..b12660eea2 100644 --- a/utils/TableGen/X86DisassemblerTables.cpp +++ b/utils/TableGen/X86DisassemblerTables.cpp @@ -642,12 +642,16 @@ void DisassemblerTables::setTableFields(OpcodeType type, InstructionContext insnContext, uint8_t opcode, const ModRMFilter &filter, - InstrUID uid) { + InstrUID uid, + bool is32bit) { unsigned index; ContextDecision &decision = *Tables[type]; for (index = 0; index < IC_max; ++index) { + if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT)) + continue; + if (inheritsFrom((InstructionContext)index, InstructionSpecifiers[uid].insnContext)) setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode], diff --git a/utils/TableGen/X86DisassemblerTables.h b/utils/TableGen/X86DisassemblerTables.h index d16ebfca41..ae126be569 100644 --- a/utils/TableGen/X86DisassemblerTables.h +++ b/utils/TableGen/X86DisassemblerTables.h @@ -260,11 +260,13 @@ public: /// @param filter - The ModRMFilter that decides which ModR/M byte values /// correspond to the desired instruction. /// @param uid - The unique ID of the instruction. + /// @param is32bit - Instructon is only 32-bit void setTableFields(OpcodeType type, InstructionContext insnContext, uint8_t opcode, const ModRMFilter &filter, - InstrUID uid); + InstrUID uid, + bool is32bit); /// specForUID - Returns the instruction specifier for a given unique /// instruction ID. Used when resolving collisions. diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index ab40222898..4118293ae5 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -231,10 +231,15 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L"); // Check for 64-bit inst which does not require REX + Is32Bit = false; Is64Bit = false; // FIXME: Is there some better way to check for In64BitMode? std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { + if (Predicates[i]->getName().find("32Bit") != Name.npos) { + Is32Bit = true; + break; + } if (Predicates[i]->getName().find("64Bit") != Name.npos) { Is64Bit = true; break; @@ -947,7 +952,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { insnContext(), currentOpcode, *filter, - UID); + UID, Is32Bit); Spec->modifierType = MODIFIER_OPCODE; Spec->modifierBase = opcodeToSet; @@ -957,14 +962,14 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { insnContext(), opcodeToSet, *filter, - UID); + UID, Is32Bit); } } else { tables.setTableFields(opcodeType, insnContext(), opcodeToSet, *filter, - UID); + UID, Is32Bit); Spec->modifierType = MODIFIER_NONE; Spec->modifierBase = opcodeToSet; diff --git a/utils/TableGen/X86RecognizableInstr.h b/utils/TableGen/X86RecognizableInstr.h index 677d9f0155..390b89e032 100644 --- a/utils/TableGen/X86RecognizableInstr.h +++ b/utils/TableGen/X86RecognizableInstr.h @@ -64,8 +64,10 @@ private: bool HasLockPrefix; /// The isCodeGenOnly filed from the record bool IsCodeGenOnly; - // Whether the instruction has the predicate "Mode64Bit" + // Whether the instruction has the predicate "In64BitMode" bool Is64Bit; + // Whether the instruction has the predicate "In32BitMode" + bool Is32Bit; /// The instruction name as listed in the tables std::string Name; |