Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().

All the sub-class bit vectors are computed when first creating the
register bank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140905 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 15 insertions, 8 deletions

diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp
index 35f247a2e3..6e98d0ca91 100644
--- a/utils/TableGen/CodeGenRegisters.cpp
+++ b/utils/TableGen/CodeGenRegisters.cpp
@@ -342,11 +342,12 @@ bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
 // 2. The RC spill size must not be smaller than our spill size.
 // 3. RC spill alignment must be compatible with ours.
 //
-bool CodeGenRegisterClass::hasSubClass(const CodeGenRegisterClass *RC) const {
-  return SpillAlignment && RC->SpillAlignment % SpillAlignment == 0 &&
-    SpillSize <= RC->SpillSize &&
-    std::includes(Members.begin(), Members.end(),
-                  RC->Members.begin(), RC->Members.end(),
+static bool testSubClass(const CodeGenRegisterClass *A,
+                         const CodeGenRegisterClass *B) {
+  return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 &&
+    A->SpillSize <= B->SpillSize &&
+    std::includes(A->getMembers().begin(), A->getMembers().end(),
+                  B->getMembers().begin(), B->getMembers().end(),
                   CodeGenRegister::Less());
 }
 
@@ -403,7 +404,7 @@ computeSubClasses(ArrayRef<CodeGenRegisterClass*> RegClasses) {
       if (RC.SubClasses.test(s))
         continue;
       CodeGenRegisterClass *SubRC = RegClasses[s];
-      if (!RC.hasSubClass(SubRC))
+      if (!testSubClass(&RC, SubRC))
         continue;
       // SubRC is a sub-class. Grap all its sub-classes so we won't have to
       // check them again.
@@ -411,7 +412,7 @@ computeSubClasses(ArrayRef<CodeGenRegisterClass*> RegClasses) {
     }
 
     // Sweep up missed clique members.  They will be immediately preceeding RC.
-    for (unsigned s = rci - 1; s && RC.hasSubClass(RegClasses[s - 1]); --s)
+    for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s)
       RC.SubClasses.set(s - 1);
   }
 
diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h
index 74cf4127a3..c3af5593c1 100644
--- a/utils/TableGen/CodeGenRegisters.h
+++ b/utils/TableGen/CodeGenRegisters.h
@@ -129,7 +129,9 @@ namespace llvm {
     // 2. The RC spill size must not be smaller than our spill size.
     // 3. RC spill alignment must be compatible with ours.
     //
-    bool hasSubClass(const CodeGenRegisterClass *RC) const;
+    bool hasSubClass(const CodeGenRegisterClass *RC) const {
+      return SubClasses.test(RC->EnumValue);
+    }
 
     // getSubClasses - Returns a constant BitVector of subclasses indexed by
     // EnumValue.
@@ -155,6 +157,10 @@ namespace llvm {
     // Return the total number of allocation orders available.
     unsigned getNumOrders() const { return 1 + AltOrders.size(); }
 
+    // Get the set of registers.  This set contains the same registers as
+    // getOrder(0).
+    const CodeGenRegister::Set &getMembers() const { return Members; }
+
     CodeGenRegisterClass(CodeGenRegBank&, Record *R);
 
     // Called by CodeGenRegBank::CodeGenRegBank().