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author | Evan Cheng <evan.cheng@apple.com> | 2009-01-22 09:10:11 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-01-22 09:10:11 +0000 |
commit | 536ab130ec95cbb7bf30530251dafa7dfecc8471 (patch) | |
tree | c971d4e06869171104e9756ab2bdab1ab0a25ed6 /utils | |
parent | e70909b8c94b18ae5fcfe8010251d2527704d58b (diff) | |
download | llvm-536ab130ec95cbb7bf30530251dafa7dfecc8471.tar.gz llvm-536ab130ec95cbb7bf30530251dafa7dfecc8471.tar.bz2 llvm-536ab130ec95cbb7bf30530251dafa7dfecc8471.tar.xz |
Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r-- | utils/TableGen/FastISelEmitter.cpp | 5 | ||||
-rw-r--r-- | utils/TableGen/RegisterInfoEmitter.cpp | 78 |
2 files changed, 3 insertions, 80 deletions
diff --git a/utils/TableGen/FastISelEmitter.cpp b/utils/TableGen/FastISelEmitter.cpp index 3ce7642598..201a2cc5fe 100644 --- a/utils/TableGen/FastISelEmitter.cpp +++ b/utils/TableGen/FastISelEmitter.cpp @@ -440,7 +440,8 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { Operands.PrintArguments(OS, *Memo.PhysRegs); OS << ");\n"; } else { - OS << "extractsubreg(Op0, "; + OS << "extractsubreg(" << getName(RetVT); + OS << ", Op0, "; OS << (unsigned)Memo.SubRegNo; OS << ");\n"; } @@ -534,7 +535,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { Operands.PrintArguments(OS, *Memo.PhysRegs); OS << ");\n"; } else { - OS << "extractsubreg(Op0, "; + OS << "extractsubreg(RetVT, Op0, "; OS << (unsigned)Memo.SubRegNo; OS << ");\n"; } diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 06f43d5d2d..67d1cfcf4d 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -240,83 +240,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { << RegisterClasses[i].getName() << "RegClass;\n"; std::map<unsigned, std::set<unsigned> > SuperClassMap; - std::map<unsigned, std::set<unsigned> > SuperRegClassMap; OS << "\n"; - - // Emit the sub-register classes for each RegisterClass - for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { - const CodeGenRegisterClass &RC = RegisterClasses[rc]; - - // Give the register class a legal C name if it's anonymous. - std::string Name = RC.TheDef->getName(); - - OS << " // " << Name - << " Sub-register Classes...\n" - << " static const TargetRegisterClass* const " - << Name << "SubRegClasses [] = {\n "; - - bool Empty = true; - - for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size(); - subrc != subrcMax; ++subrc) { - unsigned rc2 = 0, e2 = RegisterClasses.size(); - for (; rc2 != e2; ++rc2) { - const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; - if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) { - if (!Empty) - OS << ", "; - OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; - Empty = false; - - std::map<unsigned, std::set<unsigned> >::iterator SCMI = - SuperRegClassMap.find(rc2); - if (SCMI == SuperRegClassMap.end()) { - SuperRegClassMap.insert(std::make_pair(rc2, std::set<unsigned>())); - SCMI = SuperRegClassMap.find(rc2); - } - SCMI->second.insert(rc); - break; - } - } - if (rc2 == e2) - throw "Register Class member '" + - RC.SubRegClasses[subrc]->getName() + - "' is not a valid RegisterClass!"; - } - - OS << (!Empty ? ", " : "") << "NULL"; - OS << "\n };\n\n"; - } - - // Emit the super-register classes for each RegisterClass - for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { - const CodeGenRegisterClass &RC = RegisterClasses[rc]; - - // Give the register class a legal C name if it's anonymous. - std::string Name = RC.TheDef->getName(); - - OS << " // " << Name - << " Super-register Classes...\n" - << " static const TargetRegisterClass* const " - << Name << "SuperRegClasses [] = {\n "; - - bool Empty = true; - std::map<unsigned, std::set<unsigned> >::iterator I = - SuperRegClassMap.find(rc); - if (I != SuperRegClassMap.end()) { - for (std::set<unsigned>::iterator II = I->second.begin(), - EE = I->second.end(); II != EE; ++II) { - const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; - if (!Empty) - OS << ", "; - OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; - Empty = false; - } - } - - OS << (!Empty ? ", " : "") << "NULL"; - OS << "\n };\n\n"; - } // Emit the sub-classes array for each RegisterClass for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { @@ -398,8 +322,6 @@ void RegisterInfoEmitter::run(std::ostream &OS) { << RC.getName() + "VTs" << ", " << RC.getName() + "Subclasses" << ", " << RC.getName() + "Superclasses" << ", " - << RC.getName() + "SubRegClasses" << ", " - << RC.getName() + "SuperRegClasses" << ", " << RC.SpillSize/8 << ", " << RC.SpillAlignment/8 << ", " << RC.CopyCost << ", " |