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authorCraig Topper <craig.topper@gmail.com>2012-02-21 07:36:39 +0000
committerCraig Topper <craig.topper@gmail.com>2012-02-21 07:36:39 +0000
commit7d9b20792bfc528647f8bd7644934b228cc6c60b (patch)
treea79fc58997c9b6b40d65fd529e4ee1e6844de5a4 /utils
parentf3e3783012dc7875ed37be8aaaefd96f98454781 (diff)
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Reorder some members in MCRegisterClass to remove padding on 64-bit builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151043 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r--utils/TableGen/RegisterInfoEmitter.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 7e41a110e7..1193f1cc31 100644
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -391,8 +391,8 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
<< RC.SpillAlignment/8 << ", "
<< RC.CopyCost << ", "
<< RC.Allocatable << ", "
- << RC.getName() << ", " << RC.getOrder().size() << ", "
- << RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits) },\n";
+ << RC.getName() << ", " << RC.getName() << "Bits, "
+ << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits) },\n";
}
OS << "};\n\n";