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| author | Chris Lattner <sabre@nondot.org> | 2006-11-06 21:44:54 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-11-06 21:44:54 +0000 |
| commit | a818e92f8b7ac805c0c7a9747d427186048b1440 (patch) | |
| tree | fb21007be354504dce0be63a4fa868bd6f335502 /utils | |
| parent | 1b1b737d7dc7b3330331cf65514719d719f88a43 (diff) | |
| download | llvm-a818e92f8b7ac805c0c7a9747d427186048b1440.tar.gz llvm-a818e92f8b7ac805c0c7a9747d427186048b1440.tar.bz2 llvm-a818e92f8b7ac805c0c7a9747d427186048b1440.tar.xz | |
recognize ppc's blr instruction as predicated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31480 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
| -rw-r--r-- | utils/TableGen/CodeGenInstruction.h | 1 | ||||
| -rw-r--r-- | utils/TableGen/CodeGenTarget.cpp | 2 | ||||
| -rw-r--r-- | utils/TableGen/InstrInfoEmitter.cpp | 1 |
3 files changed, 4 insertions, 0 deletions
diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h index e1c4c7d6d3..26423d02ff 100644 --- a/utils/TableGen/CodeGenInstruction.h +++ b/utils/TableGen/CodeGenInstruction.h @@ -87,6 +87,7 @@ namespace llvm { bool isLoad; bool isStore; bool isTwoAddress; + bool isPredicated; bool isConvertibleToThreeAddress; bool isCommutable; bool isTerminator; diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp index f8410c17ff..5893a58623 100644 --- a/utils/TableGen/CodeGenTarget.cpp +++ b/utils/TableGen/CodeGenTarget.cpp @@ -335,6 +335,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr) isLoad = R->getValueAsBit("isLoad"); isStore = R->getValueAsBit("isStore"); isTwoAddress = R->getValueAsBit("isTwoAddress"); + isPredicated = false; // set below. isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress"); isCommutable = R->getValueAsBit("isCommutable"); isTerminator = R->getValueAsBit("isTerminator"); @@ -381,6 +382,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr) if (unsigned NumArgs = MIOpInfo->getNumArgs()) NumOps = NumArgs; + isPredicated |= Rec->isSubClassOf("PredicateOperand"); } else if (Rec->getName() == "variable_ops") { hasVariableNumberOfOperands = true; continue; diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index bf69d08523..41fb696994 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -225,6 +225,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, if (Inst.isLoad) OS << "|M_LOAD_FLAG"; if (Inst.isStore || isStore) OS << "|M_STORE_FLAG"; if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG"; + if (Inst.isPredicated) OS << "|M_PREDICATED"; if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR"; if (Inst.isCommutable) OS << "|M_COMMUTABLE"; if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG"; |