Add X86 BZHI instruction as well as BMI2 feature detection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 11 insertions, 15 deletions

diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index 6c4c584651..b3a316d6c7 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -219,6 +219,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
+  HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
   IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
@@ -261,9 +262,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
              Rec->getName().find("PUSH64") != Name.npos ||
              Rec->getName().find("POP64") != Name.npos;
 
-  // FIXME: BEXTR uses VEX.vvvv to encode its third operand
-  IsBEXTR = Rec->getName().find("BEXTR") != Name.npos;
-
   ShouldBeEmitted  = true;
 }
   
@@ -286,7 +284,7 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
 InstructionContext RecognizableInstr::insnContext() const {
   InstructionContext insnContext;
 
-  if (HasVEX_4VPrefix || HasVEXPrefix) {
+  if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
     if (HasVEX_LPrefix && HasVEX_WPrefix)
       llvm_unreachable("Don't support VEX.L and VEX.W together");
     else if (HasOpSizePrefix && HasVEX_LPrefix)
@@ -686,7 +684,7 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
     // - In AVX, there is a register operand in the VEX.vvvv field here -
     // Operand 3 (optional) is an immediate.
 
-    if (HasVEX_4VPrefix)
+    if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V"); 
     else
@@ -695,15 +693,14 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
   
     HANDLE_OPERAND(roRegister)
 
-    if (HasVEX_4VPrefix && !IsBEXTR)
+    if (HasVEX_4VPrefix)
       // FIXME: In AVX, the register below becomes the one encoded
       // in ModRMVEX and the one above the one in the VEX.VVVV field
       HANDLE_OPERAND(vvvvRegister)
 
     HANDLE_OPERAND(rmRegister)
 
-    // FIXME: BEXTR uses VEX.vvvv for Operand 3
-    if (IsBEXTR)
+    if (HasVEX_4VOp3Prefix)
       HANDLE_OPERAND(vvvvRegister)
 
     HANDLE_OPTIONAL(immediate)
@@ -713,8 +710,8 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
     // Operand 2 is a memory operand (possibly SIB-extended)
     // - In AVX, there is a register operand in the VEX.vvvv field here -
     // Operand 3 (optional) is an immediate.
-    
-    if (HasVEX_4VPrefix)
+
+    if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V"); 
     else
@@ -723,15 +720,14 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
     
     HANDLE_OPERAND(roRegister)
 
-    if (HasVEX_4VPrefix && !IsBEXTR)
+    if (HasVEX_4VPrefix)
       // FIXME: In AVX, the register below becomes the one encoded
       // in ModRMVEX and the one above the one in the VEX.VVVV field
       HANDLE_OPERAND(vvvvRegister)
 
     HANDLE_OPERAND(memory)
 
-    // FIXME: BEXTR uses VEX.vvvv for Operand 3
-    if (IsBEXTR)
+    if (HasVEX_4VOp3Prefix)
       HANDLE_OPERAND(vvvvRegister)
 
     HANDLE_OPTIONAL(immediate)
diff --git a/utils/TableGen/X86RecognizableInstr.h b/utils/TableGen/X86RecognizableInstr.h
index 7ed820b80d..42a5fec1d3 100644
--- a/utils/TableGen/X86RecognizableInstr.h
+++ b/utils/TableGen/X86RecognizableInstr.h
@@ -56,6 +56,8 @@ private:
   bool HasVEXPrefix;
   /// The hasVEX_4VPrefix field from the record
   bool HasVEX_4VPrefix;
+  /// The hasVEX_4VOp3Prefix field from the record
+  bool HasVEX_4VOp3Prefix;
   /// The hasVEX_WPrefix field from the record
   bool HasVEX_WPrefix;
   /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
@@ -70,8 +72,6 @@ private:
   bool Is64Bit;
   // Whether the instruction has the predicate "In32BitMode"
   bool Is32Bit;
-  // Whether the instruction is BEXTR
-  bool IsBEXTR;
 
   /// The instruction name as listed in the tables
   std::string Name;