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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-10-04 15:28:44 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-10-04 15:28:44 +0000 |
commit | cc0c975b7db95ce6bc865c56a3016bf0d4f83304 (patch) | |
tree | b1b775c2266ca79988883a5c6c79d7705edfe186 /utils | |
parent | 6fea31e7300fe012b0b2984d6bc0338d02b054d3 (diff) | |
download | llvm-cc0c975b7db95ce6bc865c56a3016bf0d4f83304.tar.gz llvm-cc0c975b7db95ce6bc865c56a3016bf0d4f83304.tar.bz2 llvm-cc0c975b7db95ce6bc865c56a3016bf0d4f83304.tar.xz |
TableGen: Store all allocation orders together.
There is no need to keep the primary order separate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141082 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r-- | utils/TableGen/CodeGenRegisters.cpp | 18 | ||||
-rw-r--r-- | utils/TableGen/CodeGenRegisters.h | 11 |
2 files changed, 15 insertions, 14 deletions
diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp index 0785f70ce0..b3bd81e8a6 100644 --- a/utils/TableGen/CodeGenRegisters.cpp +++ b/utils/TableGen/CodeGenRegisters.cpp @@ -273,18 +273,22 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) } assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!"); + // Allocation order 0 is the full set. AltOrders provides others. + const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); + ListInit *AltOrders = R->getValueAsListInit("AltOrders"); + Orders.resize(1 + AltOrders->size()); + // Default allocation order always contains all registers. - Elements = RegBank.getSets().expand(R); - for (unsigned i = 0, e = Elements->size(); i != e; ++i) + for (unsigned i = 0, e = Elements->size(); i != e; ++i) { + Orders[0].push_back((*Elements)[i]); Members.insert(RegBank.getReg((*Elements)[i])); + } // Alternative allocation orders may be subsets. - ListInit *Alts = R->getValueAsListInit("AltOrders"); - AltOrders.resize(Alts->size()); SetTheory::RecSet Order; - for (unsigned i = 0, e = Alts->size(); i != e; ++i) { - RegBank.getSets().evaluate(Alts->getElement(i), Order); - AltOrders[i].append(Order.begin(), Order.end()); + for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { + RegBank.getSets().evaluate(AltOrders->getElement(i), Order); + Orders[1 + i].append(Order.begin(), Order.end()); // Verify that all altorder members are regclass members. while (!Order.empty()) { CodeGenRegister *Reg = RegBank.getReg(Order.back()); diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index b8d2053cf9..6e8d6c04e0 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -86,8 +86,8 @@ namespace llvm { class CodeGenRegisterClass { CodeGenRegister::Set Members; - const std::vector<Record*> *Elements; - std::vector<SmallVector<Record*, 16> > AltOrders; + // Allocation orders. Order[0] always contains all registers in Members. + std::vector<SmallVector<Record*, 16> > Orders; // Bit mask of sub-classes including this, indexed by their EnumValue. BitVector SubClasses; // List of super-classes, topologocally ordered to have the larger classes @@ -154,14 +154,11 @@ namespace llvm { // The order of registers is the same as in the .td file. // No = 0 is the default allocation order, No = 1 is the first alternative. ArrayRef<Record*> getOrder(unsigned No = 0) const { - if (No == 0) - return *Elements; - else - return AltOrders[No - 1]; + return Orders[No]; } // Return the total number of allocation orders available. - unsigned getNumOrders() const { return 1 + AltOrders.size(); } + unsigned getNumOrders() const { return Orders.size(); } // Get the set of registers. This set contains the same registers as // getOrder(0). |