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authorCraig Topper <craig.topper@gmail.com>2012-09-16 16:35:22 +0000
committerCraig Topper <craig.topper@gmail.com>2012-09-16 16:35:22 +0000
commitef2340ef4848065f74f9b98c5d392028392d7cae (patch)
tree06af710057d81a9127a05a969c24d0ce04a1ffc0 /utils
parent6fc671ca637e83d53f47c913e9e0ac8e2cce3a51 (diff)
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Add 'virtual' keywoards to output file for overridden functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163999 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r--utils/TableGen/RegisterInfoEmitter.cpp14
1 files changed, 7 insertions, 7 deletions
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 42b213c04a..87624665cb 100644
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -802,16 +802,16 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
<< " virtual bool needsStackRealignment(const MachineFunction &) const\n"
<< " { return false; }\n";
if (!RegBank.getSubRegIndices().empty()) {
- OS << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
- << " const TargetRegisterClass *"
+ OS << " virtual unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
+ << " virtual const TargetRegisterClass *"
"getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n";
}
- OS << " const RegClassWeight &getRegClassWeight("
+ OS << " virtual const RegClassWeight &getRegClassWeight("
<< "const TargetRegisterClass *RC) const;\n"
- << " unsigned getNumRegPressureSets() const;\n"
- << " const char *getRegPressureSetName(unsigned Idx) const;\n"
- << " unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
- << " const int *getRegClassPressureSets("
+ << " virtual unsigned getNumRegPressureSets() const;\n"
+ << " virtual const char *getRegPressureSetName(unsigned Idx) const;\n"
+ << " virtual unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
+ << " virtual const int *getRegClassPressureSets("
<< "const TargetRegisterClass *RC) const;\n"
<< "};\n\n";