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author | Bill Wendling <isanbard@gmail.com> | 2010-12-14 03:36:38 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2010-12-14 03:36:38 +0000 |
commit | f4caf69720d807573c50d41aa06bcec1c99bdbbd (patch) | |
tree | bdf33e0c29180acbfd4f2f74dcfd78e3d1866bdf /utils | |
parent | 0c1aec18911f2a67fb37b6593d08f4f8cb7e18ef (diff) | |
download | llvm-f4caf69720d807573c50d41aa06bcec1c99bdbbd.tar.gz llvm-f4caf69720d807573c50d41aa06bcec1c99bdbbd.tar.bz2 llvm-f4caf69720d807573c50d41aa06bcec1c99bdbbd.tar.xz |
The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r-- | utils/TableGen/EDEmitter.cpp | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp index 9c27515ec7..8e37519af0 100644 --- a/utils/TableGen/EDEmitter.cpp +++ b/utils/TableGen/EDEmitter.cpp @@ -629,9 +629,12 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type, MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset"); // R, I MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I - MISC("t_addrmode_s1", "kOperandTypeThumbAddrModeS1"); // R, I, R - MISC("t_addrmode_s2", "kOperandTypeThumbAddrModeS2"); // R, I, R - MISC("t_addrmode_s4", "kOperandTypeThumbAddrModeS4"); // R, I, R + MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS"); // R, R + MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS"); // R, R + MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS"); // R, R + MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS"); // R, I + MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS"); // R, I + MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS"); // R, I MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC"); // R, I @@ -841,9 +844,8 @@ static void emitCommonEnums(raw_ostream &o, unsigned int &i) { operandTypes.addEntry("kOperandTypeARMSPRRegisterList"); operandTypes.addEntry("kOperandTypeARMTBAddrMode"); operandTypes.addEntry("kOperandTypeThumbITMask"); - operandTypes.addEntry("kOperandTypeThumbAddrModeS1"); - operandTypes.addEntry("kOperandTypeThumbAddrModeS2"); - operandTypes.addEntry("kOperandTypeThumbAddrModeS4"); + operandTypes.addEntry("kOperandTypeThumbAddrModeRegS"); + operandTypes.addEntry("kOperandTypeThumbAddrModeImmS"); operandTypes.addEntry("kOperandTypeThumbAddrModeRR"); operandTypes.addEntry("kOperandTypeThumbAddrModeSP"); operandTypes.addEntry("kOperandTypeThumbAddrModePC"); |