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-rw-r--r--include/llvm/Target/Target.td5
-rw-r--r--lib/Target/ARM/ARMRegisterInfo.td154
-rw-r--r--lib/Target/Blackfin/BlackfinRegisterInfo.td8
-rw-r--r--lib/Target/MSP430/MSP430RegisterInfo.td10
-rw-r--r--lib/Target/Mips/MipsRegisterInfo.td16
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.td20
-rw-r--r--lib/Target/SystemZ/SystemZRegisterInfo.td32
-rw-r--r--lib/Target/X86/X86RegisterInfo.td126
-rw-r--r--utils/TableGen/RegisterInfoEmitter.cpp15
9 files changed, 197 insertions, 189 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index b9ec987cd1..5fd69cf2e6 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -21,6 +21,7 @@ include "llvm/Intrinsics.td"
class RegisterClass; // Forward def
+// SubRegIndex - Use instances on SubRegIndex to identify subregisters.
class SubRegIndex {
string Namespace = "";
@@ -80,8 +81,8 @@ class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
// indices, for use as named subregs of a particular physical register. Each
// register in 'subregs' becomes an addressable subregister at index 'n' of the
// corresponding register in 'regs'.
-class SubRegSet<int n, list<Register> regs, list<Register> subregs> {
- int index = n;
+class SubRegSet<SubRegIndex n, list<Register> regs, list<Register> subregs> {
+ SubRegIndex Index = n;
list<Register> From = regs;
list<Register> To = subregs;
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index d16d0a784d..a71cf7235c 100644
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -444,96 +444,96 @@ def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
//
// S sub-registers of D registers.
-def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
- D8, D9, D10, D11, D12, D13, D14, D15],
- [S0, S2, S4, S6, S8, S10, S12, S14,
- S16, S18, S20, S22, S24, S26, S28, S30]>;
-def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7,
- D8, D9, D10, D11, D12, D13, D14, D15],
- [S1, S3, S5, S7, S9, S11, S13, S15,
- S17, S19, S21, S23, S25, S27, S29, S31]>;
+def : SubRegSet<ssub_0, [D0, D1, D2, D3, D4, D5, D6, D7,
+ D8, D9, D10, D11, D12, D13, D14, D15],
+ [S0, S2, S4, S6, S8, S10, S12, S14,
+ S16, S18, S20, S22, S24, S26, S28, S30]>;
+def : SubRegSet<ssub_1, [D0, D1, D2, D3, D4, D5, D6, D7,
+ D8, D9, D10, D11, D12, D13, D14, D15],
+ [S1, S3, S5, S7, S9, S11, S13, S15,
+ S17, S19, S21, S23, S25, S27, S29, S31]>;
// S sub-registers of Q registers.
-def : SubRegSet<1, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
- [S0, S4, S8, S12, S16, S20, S24, S28]>;
-def : SubRegSet<2, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
- [S1, S5, S9, S13, S17, S21, S25, S29]>;
-def : SubRegSet<3, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
- [S2, S6, S10, S14, S18, S22, S26, S30]>;
-def : SubRegSet<4, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
- [S3, S7, S11, S15, S19, S23, S27, S31]>;
+def : SubRegSet<ssub_0, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
+ [S0, S4, S8, S12, S16, S20, S24, S28]>;
+def : SubRegSet<ssub_1, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
+ [S1, S5, S9, S13, S17, S21, S25, S29]>;
+def : SubRegSet<ssub_2, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
+ [S2, S6, S10, S14, S18, S22, S26, S30]>;
+def : SubRegSet<ssub_3, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
+ [S3, S7, S11, S15, S19, S23, S27, S31]>;
// D sub-registers of Q registers.
-def : SubRegSet<5, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
- Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
- [D0, D2, D4, D6, D8, D10, D12, D14,
- D16, D18, D20, D22, D24, D26, D28, D30]>;
-def : SubRegSet<6, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
- Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
- [D1, D3, D5, D7, D9, D11, D13, D15,
- D17, D19, D21, D23, D25, D27, D29, D31]>;
+def : SubRegSet<dsub_0, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
+ Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
+ [D0, D2, D4, D6, D8, D10, D12, D14,
+ D16, D18, D20, D22, D24, D26, D28, D30]>;
+def : SubRegSet<dsub_1, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
+ Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
+ [D1, D3, D5, D7, D9, D11, D13, D15,
+ D17, D19, D21, D23, D25, D27, D29, D31]>;
// S sub-registers of QQ registers. Note there are no sub-indices
// for referencing S4 - S7, S12 - S15, and S20 - S23. It doesn't
// look like we need them.
-def : SubRegSet<1, [QQ0, QQ1, QQ2, QQ3],
- [S0, S8, S16, S24]>;
-def : SubRegSet<2, [QQ0, QQ1, QQ2, QQ3],
- [S1, S9, S17, S25]>;
-def : SubRegSet<3, [QQ0, QQ1, QQ2, QQ3],
- [S2, S10, S18, S26]>;
-def : SubRegSet<4, [QQ0, QQ1, QQ2, QQ3],
- [S3, S11, S19, S27]>;
+def : SubRegSet<ssub_0, [QQ0, QQ1, QQ2, QQ3],
+ [S0, S8, S16, S24]>;
+def : SubRegSet<ssub_1, [QQ0, QQ1, QQ2, QQ3],
+ [S1, S9, S17, S25]>;
+def : SubRegSet<ssub_2, [QQ0, QQ1, QQ2, QQ3],
+ [S2, S10, S18, S26]>;
+def : SubRegSet<ssub_3, [QQ0, QQ1, QQ2, QQ3],
+ [S3, S11, S19, S27]>;
// D sub-registers of QQ registers.
-def : SubRegSet<5, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
- [D0, D4, D8, D12, D16, D20, D24, D28]>;
-def : SubRegSet<6, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
- [D1, D5, D9, D13, D17, D21, D25, D29]>;
-def : SubRegSet<7, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
- [D2, D6, D10, D14, D18, D22, D26, D30]>;
-def : SubRegSet<8, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
- [D3, D7, D11, D15, D19, D23, D27, D31]>;
+def : SubRegSet<dsub_0, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
+ [D0, D4, D8, D12, D16, D20, D24, D28]>;
+def : SubRegSet<dsub_1, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
+ [D1, D5, D9, D13, D17, D21, D25, D29]>;
+def : SubRegSet<dsub_2, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
+ [D2, D6, D10, D14, D18, D22, D26, D30]>;
+def : SubRegSet<dsub_3, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
+ [D3, D7, D11, D15, D19, D23, D27, D31]>;
// Q sub-registers of QQ registers.
-def : SubRegSet<13, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
- [Q0, Q2, Q4, Q6, Q8, Q10, Q12, Q14]>;
-def : SubRegSet<14,[QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
- [Q1, Q3, Q5, Q7, Q9, Q11, Q13, Q15]>;
+def : SubRegSet<qsub_0, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
+ [Q0, Q2, Q4, Q6, Q8, Q10, Q12, Q14]>;
+def : SubRegSet<qsub_1,[QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
+ [Q1, Q3, Q5, Q7, Q9, Q11, Q13, Q15]>;
// D sub-registers of QQQQ registers.
-def : SubRegSet<5, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [D0, D8, D16, D24]>;
-def : SubRegSet<6, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [D1, D9, D17, D25]>;
-def : SubRegSet<7, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [D2, D10, D18, D26]>;
-def : SubRegSet<8, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [D3, D11, D19, D27]>;
-
-def : SubRegSet<9, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [D4, D12, D20, D28]>;
-def : SubRegSet<10, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [D5, D13, D21, D29]>;
-def : SubRegSet<11, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [D6, D14, D22, D30]>;
-def : SubRegSet<12, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [D7, D15, D23, D31]>;
-
-// Q sub-registers of QQQQQQQQ registers.
-def : SubRegSet<13, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [Q0, Q4, Q8, Q12]>;
-def : SubRegSet<14, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [Q1, Q5, Q9, Q13]>;
-def : SubRegSet<15, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [Q2, Q6, Q10, Q14]>;
-def : SubRegSet<16, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [Q3, Q7, Q11, Q15]>;
-
-// QQ sub-registers of QQQQQQQQ registers.
-def : SubRegSet<17, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [QQ0, QQ2, QQ4, QQ6]>;
-def : SubRegSet<18, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
- [QQ1, QQ3, QQ5, QQ7]>;
+def : SubRegSet<dsub_0, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D0, D8, D16, D24]>;
+def : SubRegSet<dsub_1, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D1, D9, D17, D25]>;
+def : SubRegSet<dsub_2, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D2, D10, D18, D26]>;
+def : SubRegSet<dsub_3, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D3, D11, D19, D27]>;
+
+def : SubRegSet<dsub_4, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D4, D12, D20, D28]>;
+def : SubRegSet<dsub_5, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D5, D13, D21, D29]>;
+def : SubRegSet<dsub_6, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D6, D14, D22, D30]>;
+def : SubRegSet<dsub_7, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D7, D15, D23, D31]>;
+
+// Q sub-registers of QQQQ registers.
+def : SubRegSet<qsub_0, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [Q0, Q4, Q8, Q12]>;
+def : SubRegSet<qsub_1, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [Q1, Q5, Q9, Q13]>;
+def : SubRegSet<qsub_2, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [Q2, Q6, Q10, Q14]>;
+def : SubRegSet<qsub_3, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [Q3, Q7, Q11, Q15]>;
+
+// QQ sub-registers of QQQQ registers.
+def : SubRegSet<qqsub_0, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [QQ0, QQ2, QQ4, QQ6]>;
+def : SubRegSet<qqsub_1, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [QQ1, QQ3, QQ5, QQ7]>;
diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.td b/lib/Target/Blackfin/BlackfinRegisterInfo.td
index 09c5d754e4..d47f6b13fd 100644
--- a/lib/Target/Blackfin/BlackfinRegisterInfo.td
+++ b/lib/Target/Blackfin/BlackfinRegisterInfo.td
@@ -191,7 +191,7 @@ def LC1 : Ri<6, 3, "lc1">, DwarfRegNum<[47]>;
def LB0 : Ri<6, 2, "lb0">, DwarfRegNum<[48]>;
def LB1 : Ri<6, 5, "lb1">, DwarfRegNum<[49]>;
-def : SubRegSet<1,
+def : SubRegSet<lo16,
[R0, R1, R2, R3, R4, R5, R6, R7,
P0, P1, P2, P3, P4, P5, SP, FP,
I0, I1, I2, I3, M0, M1, M2, M3,
@@ -201,7 +201,7 @@ def : SubRegSet<1,
I0L, I1L, I2L, I3L, M0L, M1L, M2L, M3L,
B0L, B1L, B2L, B3L, L0L, L1L, L2L, L3L]>;
-def : SubRegSet<2,
+def : SubRegSet<hi16,
[R0, R1, R2, R3, R4, R5, R6, R7,
P0, P1, P2, P3, P4, P5, SP, FP,
I0, I1, I2, I3, M0, M1, M2, M3,
@@ -211,8 +211,8 @@ def : SubRegSet<2,
I0H, I1H, I2H, I3H, M0H, M1H, M2H, M3H,
B0H, B1H, B2H, B3H, L0H, L1H, L2H, L3H]>;
-def : SubRegSet<1, [A0, A0W, A1, A1W], [A0L, A0L, A1L, A1L]>;
-def : SubRegSet<2, [A0, A0W, A1, A1W], [A0H, A0H, A1H, A1H]>;
+def : SubRegSet<lo16, [A0, A0W, A1, A1W], [A0L, A0L, A1L, A1L]>;
+def : SubRegSet<hi16, [A0, A0W, A1, A1W], [A0H, A0H, A1H, A1H]>;
// Register classes.
def D16 : RegisterClass<"BF", [i16], 16,
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td
index bacc1c0506..80db8b069a 100644
--- a/lib/Target/MSP430/MSP430RegisterInfo.td
+++ b/lib/Target/MSP430/MSP430RegisterInfo.td
@@ -60,16 +60,16 @@ def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>;
def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>;
def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>;
-def : SubRegSet<1, [PCW, SPW, SRW, CGW, FPW,
- R5W, R6W, R7W, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
- [PCB, SPB, SRB, CGB, FPB,
- R5B, R6B, R7B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
-
def subreg_8bit : SubRegIndex {
let NumberHack = 1;
let Namespace = "MSP430";
}
+def : SubRegSet<subreg_8bit, [PCW, SPW, SRW, CGW, FPW, R5W, R6W, R7W,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
+ [PCB, SPB, SRB, CGB, FPB, R5B, R6B, R7B,
+ R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
def GR8 : RegisterClass<"MSP430", [i8], 8,
// Volatile registers
[R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B,
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index b024ecd1fb..b9c75a6912 100644
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -149,15 +149,15 @@ def sub_fpeven : SubRegIndex { let NumberHack = 1; }
def sub_fpodd : SubRegIndex { let NumberHack = 2; }
}
-def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
- D8, D9, D10, D11, D12, D13, D14, D15],
- [F0, F2, F4, F6, F8, F10, F12, F14,
- F16, F18, F20, F22, F24, F26, F28, F30]>;
+def : SubRegSet<sub_fpeven, [D0, D1, D2, D3, D4, D5, D6, D7,
+ D8, D9, D10, D11, D12, D13, D14, D15],
+ [F0, F2, F4, F6, F8, F10, F12, F14,
+ F16, F18, F20, F22, F24, F26, F28, F30]>;
-def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7,
- D8, D9, D10, D11, D12, D13, D14, D15],
- [F1, F3, F5, F7, F9, F11, F13, F15,
- F17, F19, F21, F23, F25, F27, F29, F31]>;
+def : SubRegSet<sub_fpodd, [D0, D1, D2, D3, D4, D5, D6, D7,
+ D8, D9, D10, D11, D12, D13, D14, D15],
+ [F1, F3, F5, F7, F9, F11, F13, F15,
+ F17, F19, F21, F23, F25, F27, F29, F31]>;
//===----------------------------------------------------------------------===//
// Register Classes
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index 632ae19669..ca0e95f9c3 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -241,14 +241,18 @@ def sub_eq : SubRegIndex { let NumberHack = 3; }
def sub_un : SubRegIndex { let NumberHack = 4; }
}
-def : SubRegSet<1, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
- [CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>;
-def : SubRegSet<2, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
- [CR0GT, CR1GT, CR2GT, CR3GT, CR4GT, CR5GT, CR6GT, CR7GT]>;
-def : SubRegSet<3, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
- [CR0EQ, CR1EQ, CR2EQ, CR3EQ, CR4EQ, CR5EQ, CR6EQ, CR7EQ]>;
-def : SubRegSet<4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
- [CR0UN, CR1UN, CR2UN, CR3UN, CR4UN, CR5UN, CR6UN, CR7UN]>;
+def : SubRegSet<sub_lt,
+ [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
+ [CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>;
+def : SubRegSet<sub_gt,
+ [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
+ [CR0GT, CR1GT, CR2GT, CR3GT, CR4GT, CR5GT, CR6GT, CR7GT]>;
+def : SubRegSet<sub_eq,
+ [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
+ [CR0EQ, CR1EQ, CR2EQ, CR3EQ, CR4EQ, CR5EQ, CR6EQ, CR7EQ]>;
+def : SubRegSet<sub_un,
+ [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
+ [CR0UN, CR1UN, CR2UN, CR3UN, CR4UN, CR5UN, CR6UN, CR7UN]>;
// Link register
def LR : SPR<8, "lr">, DwarfRegNum<[65]>;
diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td
index 6b9924dca2..8288e727e6 100644
--- a/lib/Target/SystemZ/SystemZRegisterInfo.td
+++ b/lib/Target/SystemZ/SystemZRegisterInfo.td
@@ -153,28 +153,28 @@ def subreg_even : SubRegIndex { let NumberHack = 3; }
def subreg_odd : SubRegIndex { let NumberHack = 4; }
}
-def : SubRegSet<1, [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D,
- R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
- [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W,
- R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
+def : SubRegSet<subreg_32bit, [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D,
+ R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
+ [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
-def : SubRegSet<3, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
- [R0D, R2D, R4D, R6D, R8D, R10D, R12D, R14D]>;
+def : SubRegSet<subreg_even, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+ [R0D, R2D, R4D, R6D, R8D, R10D, R12D, R14D]>;
-def : SubRegSet<4, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
- [R1D, R3D, R5D, R7D, R9D, R11D, R13D, R15D]>;
+def : SubRegSet<subreg_odd, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+ [R1D, R3D, R5D, R7D, R9D, R11D, R13D, R15D]>;
-def : SubRegSet<1, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
- [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
+def : SubRegSet<subreg_even32, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
+ [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
-def : SubRegSet<2, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
- [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
+def : SubRegSet<subreg_odd32, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
+ [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
-def : SubRegSet<1, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
- [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
+def : SubRegSet<subreg_even32, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+ [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
-def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
- [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
+def : SubRegSet<subreg_odd32, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+ [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
/// Register classes
def GR32 : RegisterClass<"SystemZ", [i32], 32,
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index ac2c9a4592..551260ffcf 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -235,69 +235,69 @@ let Namespace = "X86" in {
// sub registers for each register.
//
-def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
- R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
- [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
- R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
-
-def : SubRegSet<2, [AX, CX, DX, BX],
- [AH, CH, DH, BH]>;
-
-def : SubRegSet<1, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
- R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
- [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
- R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
-
-def : SubRegSet<2, [EAX, ECX, EDX, EBX],
- [AH, CH, DH, BH]>;
-
-def : SubRegSet<3, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
- R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
- [AX, CX, DX, BX, SP, BP, SI, DI,
- R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
-
-def : SubRegSet<1, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
- R8, R9, R10, R11, R12, R13, R14, R15],
- [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
- R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
-
-def : SubRegSet<2, [RAX, RCX, RDX, RBX],
- [AH, CH, DH, BH]>;
-
-def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
- R8, R9, R10, R11, R12, R13, R14, R15],
- [AX, CX, DX, BX, SP, BP, SI, DI,
- R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
-
-def : SubRegSet<4, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
- R8, R9, R10, R11, R12, R13, R14, R15],
- [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
- R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
-
-def : SubRegSet<1, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
- YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
- [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
- XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
-
-def : SubRegSet<2, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
- YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
- [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
- XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
-
-def : SubRegSet<3, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
- YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
- [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
- XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
-
-def : SubRegSet<1, [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
- XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15],
- [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
- XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
-
-def : SubRegSet<2, [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
- XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15],
- [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
- XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
+def : SubRegSet<sub_8bit, [AX, CX, DX, BX, SP, BP, SI, DI,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
+ [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
+ R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
+def : SubRegSet<sub_8bit_hi, [AX, CX, DX, BX],
+ [AH, CH, DH, BH]>;
+
+def : SubRegSet<sub_8bit, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
+ R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
+ [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
+ R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
+def : SubRegSet<sub_8bit_hi, [EAX, ECX, EDX, EBX],
+ [AH, CH, DH, BH]>;
+
+def : SubRegSet<sub_16bit, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
+ R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
+ [AX, CX, DX, BX, SP, BP, SI, DI,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
+
+def : SubRegSet<sub_8bit, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
+ R8, R9, R10, R11, R12, R13, R14, R15],
+ [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
+ R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
+def : SubRegSet<sub_8bit_hi, [RAX, RCX, RDX, RBX],
+ [AH, CH, DH, BH]>;
+
+def : SubRegSet<sub_16bit, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
+ R8, R9, R10, R11, R12, R13, R14, R15],
+ [AX, CX, DX, BX, SP, BP, SI, DI,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
+
+def : SubRegSet<sub_32bit, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
+ R8, R9, R10, R11, R12, R13, R14, R15],
+ [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
+ R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
+
+def : SubRegSet<sub_ss, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
+ YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
+
+def : SubRegSet<sub_sd, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
+ YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
+
+def : SubRegSet<sub_xmm, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
+ YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
+
+def : SubRegSet<sub_ss, [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15],
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
+
+def : SubRegSet<sub_sd, [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15],
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
//===----------------------------------------------------------------------===//
// Register Class Definitions... now that we have all of the pieces, define the
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 0b0bf0e102..85daa15f37 100644
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -456,7 +456,8 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
- std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
+ // Register -> [(SubRegIndex, Register)]
+ std::map<Record*, std::vector<std::pair<Record*, Record*> > > SubRegVectors;
typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
DwarfRegNumsMapTy DwarfRegNums;
@@ -818,7 +819,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
// Calculate the mapping of subregister+index pairs to physical registers.
std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
- int subRegIndex = SubRegs[i]->getValueAsInt("index");
+ Record *subRegIndex = SubRegs[i]->getValueAsDef("Index");
std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
@@ -839,13 +840,14 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
<< "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
<< " switch (RegNo) {\n"
<< " default:\n return 0;\n";
- for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
+ for (std::map<Record*, std::vector<std::pair<Record*, Record*> > >::iterator
I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
OS << " case " << getQualifiedName(I->first) << ":\n";
OS << " switch (Index) {\n";
OS << " default: return 0;\n";
for (unsigned i = 0, e = I->second.size(); i != e; ++i)
- OS << " case " << (I->second)[i].first << ": return "
+ OS << " case "
+ << getQualifiedName((I->second)[i].first) << ": return "
<< getQualifiedName((I->second)[i].second) << ";\n";
OS << " };\n" << " break;\n";
}
@@ -857,13 +859,14 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
<< "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
<< " switch (RegNo) {\n"
<< " default:\n return 0;\n";
- for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
+ for (std::map<Record*, std::vector<std::pair<Record*, Record*> > >::iterator
I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
OS << " case " << getQualifiedName(I->first) << ":\n";
for (unsigned i = 0, e = I->second.size(); i != e; ++i)
OS << " if (SubRegNo == "
<< getQualifiedName((I->second)[i].second)
- << ") return " << (I->second)[i].first << ";\n";
+ << ") return "
+ << getQualifiedName((I->second)[i].first) << ";\n";
OS << " return 0;\n";
}
OS << " };\n";
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-05 08:18:22 +0000