diff options
| -rw-r--r-- | lib/Target/Sparc/SparcISelLowering.cpp | 4 | ||||
| -rw-r--r-- | test/CodeGen/SPARC/atomics.ll | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 85a02edc0a..b555049666 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -2977,7 +2977,7 @@ SparcTargetLowering::expandAtomicRMW(MachineInstr *MI, // loop: // %val = phi %val0, %dest // %upd = op %val, %rs2 - // %dest = cas %addr, %upd, %val + // %dest = cas %addr, %val, %upd // cmp %val, %dest // bne loop // done: @@ -3036,7 +3036,7 @@ SparcTargetLowering::expandAtomicRMW(MachineInstr *MI, } BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg) - .addReg(AddrReg).addReg(UpdReg).addReg(ValReg) + .addReg(AddrReg).addReg(ValReg).addReg(UpdReg) .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg); BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND)) diff --git a/test/CodeGen/SPARC/atomics.ll b/test/CodeGen/SPARC/atomics.ll index 3d0be28acc..6d2b48287c 100644 --- a/test/CodeGen/SPARC/atomics.ll +++ b/test/CodeGen/SPARC/atomics.ll @@ -64,8 +64,8 @@ entry: ; CHECK-LABEL: test_load_add_32 ; CHECK: membar -; CHECK: add -; CHECK: cas [%o0] +; CHECK: add [[V:%[gilo][0-7]]], %o1, [[U:%[gilo][0-7]]] +; CHECK: cas [%o0], [[V]], [[U]] ; CHECK: membar define zeroext i32 @test_load_add_32(i32* %p, i32 zeroext %v) { entry: |