diff options
| -rw-r--r-- | lib/Target/CellSPU/SPUISelDAGToDAG.cpp | 10 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/loads.ll | 13 |
2 files changed, 15 insertions, 8 deletions
diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index 9afdb2b97f..bfb57d3613 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -611,13 +611,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base, if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) { // Direct load/store without getelementptr - SDValue Addr, Offs; - - // Get the register from CopyFromReg - if (Opc == ISD::CopyFromReg) - Addr = N.getOperand(1); - else - Addr = N; // Register + SDValue Offs; Offs = ((OpOpc == ISD::STORE) ? Op->getOperand(3) : Op->getOperand(2)); @@ -626,7 +620,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base, Offs = CurDAG->getTargetConstant(0, Offs.getValueType()); Base = Offs; - Index = Addr; + Index = N; return true; } } else { diff --git a/test/CodeGen/CellSPU/loads.ll b/test/CodeGen/CellSPU/loads.ll index 8e5422c58e..37c6d4f151 100644 --- a/test/CodeGen/CellSPU/loads.ll +++ b/test/CodeGen/CellSPU/loads.ll @@ -18,3 +18,16 @@ entry: ret <4 x float> %tmp1 ; CHECK: lqd $3, 16($3) } + + +declare <4 x i32>* @getv4f32ptr() +define <4 x i32> @func() { + ;CHECK: brasl + ;CHECK: lr {{\$[0-9]*, \$3}} + ;CHECK: brasl + %rv1 = call <4 x i32>* @getv4f32ptr() + %rv2 = call <4 x i32>* @getv4f32ptr() + %rv3 = load <4 x i32>* %rv1 + ret <4 x i32> %rv3 +} + |