diff options
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 20 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/minsize-imms.ll | 57 |
4 files changed, 70 insertions, 11 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 8e236e16fe..d561db2f07 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -2472,19 +2472,21 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) { case ISD::Constant: { unsigned Val = cast<ConstantSDNode>(N)->getZExtValue(); bool UseCP = true; - if (Subtarget->hasThumb2()) + if (Subtarget->useMovt()) // Thumb2-aware targets have the MOVT instruction, so all immediates can // be done with MOV + MOVT, at worst. - UseCP = 0; + UseCP = false; else { if (Subtarget->isThumb()) { - UseCP = (Val > 255 && // MOV - ~Val > 255 && // MOV + MVN - !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL + UseCP = (Val > 255 && // MOV + ~Val > 255 && // MOV + MVN + !ARM_AM::isThumbImmShiftedVal(Val) && // MOV + LSL + !(Subtarget->hasV6T2Ops() && Val <= 0xffff)); // MOVW } else - UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV - ARM_AM::getSOImmVal(~Val) == -1 && // MVN - !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs. + UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV + ARM_AM::getSOImmVal(~Val) == -1 && // MVN + !ARM_AM::isSOImmTwoPartVal(Val) && // two instrs. + !(Subtarget->hasV6T2Ops() && Val <= 0xffff)); // MOVW } if (UseCP) { @@ -2494,7 +2496,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) { getTargetLowering()->getPointerTy()); SDNode *ResNode; - if (Subtarget->isThumb1Only()) { + if (Subtarget->isThumb()) { SDValue Pred = getAL(CurDAG); SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 6b93b945df..9faa4cd840 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -593,7 +593,7 @@ def so_imm2part : PatLeaf<(imm), [{ /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true. /// def arm_i32imm : PatLeaf<(imm), [{ - if (Subtarget->hasV6T2Ops()) + if (Subtarget->useMovt()) return true; return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); }]>; diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 73dc071e77..dd53ff6ccf 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -3781,7 +3781,7 @@ def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary, let isReMaterializable = 1, isMoveImm = 1 in def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2, [(set rGPR:$dst, (i32 imm:$src))]>, - Requires<[IsThumb, HasV6T2]>; + Requires<[IsThumb, UseMovt]>; // Pseudo instruction that combines movw + movt + add pc (if pic). // It also makes it possible to rematerialize the instructions. diff --git a/test/CodeGen/ARM/minsize-imms.ll b/test/CodeGen/ARM/minsize-imms.ll new file mode 100644 index 0000000000..4c8ff393a4 --- /dev/null +++ b/test/CodeGen/ARM/minsize-imms.ll @@ -0,0 +1,57 @@ +; RUN: llc -mtriple=thumbv7m-macho -o - -show-mc-encoding %s | FileCheck %s +; RUN: llc -mtriple=thumbv6m-macho -o - -show-mc-encoding %s | FileCheck %s --check-prefix=CHECK-V6M +; RUN: llc -mtriple=armv6-macho -o - -show-mc-encoding %s | FileCheck %s --check-prefix=CHECK-ARM +define i32 @test_mov() minsize { +; CHECK-LABEL: test_mov: +; CHECK: movs r0, #255 @ encoding: [0xff,0x20] + + ret i32 255 +} + +define i32 @test_mov_mvn() minsize { +; CHECK-LABEL: test_mov_mvn: +; CHECK: mvn r0, #203 @ encoding: [0x6f,0xf0,0xcb,0x00] + +; CHECK-V6M-LABEL: test_mov_mvn: +; CHECK-V6M: movs [[TMP:r[0-7]]], #203 @ encoding: [0xcb,0x20] +; CHECK-V6M: mvns r0, [[TMP]] @ encoding: [0xc0,0x43] + +; CHECK-ARM-LABEL: test_mov_mvn: +; CHECK-ARM: mvn r0, #203 @ encoding: [0xcb,0x00,0xe0,0xe3] + ret i32 4294967092 +} + +define i32 @test_mov_lsl() minsize { +; CHECK-LABEL: test_mov_lsl: +; CHECK: mov.w r0, #589824 @ encoding: [0x4f,0xf4,0x10,0x20] + +; CHECK-V6M-LABEL: test_mov_lsl: +; CHECK-V6M: movs [[TMP:r[0-7]]], #9 @ encoding: [0x09,0x20] +; CHECK-V6M: lsls r0, [[TMP]], #16 @ encoding: [0x00,0x04] + +; CHECK-ARM-LABEL: test_mov_lsl: +; CHECK-ARM: mov r0, #589824 @ encoding: [0x09,0x08,0xa0,0xe3] + ret i32 589824 +} + +define i32 @test_movw() minsize { +; CHECK-LABEL: test_movw: +; CHECK: movw r0, #65535 + +; CHECK-V6M-LABEL: test_movw: +; CHECK-V6M: ldr r0, [[CONSTPOOL:LCPI[0-9]+_[0-9]+]] @ encoding: [A,0x48] +; CHECK-V6M: [[CONSTPOOL]]: +; CHECK-V6M-NEXT: .long 65535 + +; CHECK-ARM-LABEL: test_movw: +; CHECK-ARM: mov r0, #255 @ encoding: [0xff,0x00,0xa0,0xe3] +; CHECK-ARM: orr r0, r0, #65280 @ encoding: [0xff,0x0c,0x80,0xe3] + ret i32 65535 +} + +define i32 @test_regress1() { +; CHECK-ARM-LABEL: test_regress1: +; CHECK-ARM: mov r0, #248 @ encoding: [0xf8,0x00,0xa0,0xe3] +; CHECK-ARM: orr r0, r0, #16252928 @ encoding: [0x3e,0x07,0x80,0xe3] + ret i32 16253176 +} |