diff options
| -rw-r--r-- | lib/Target/R600/AMDGPU.td | 12 | ||||
| -rw-r--r-- | lib/Target/R600/AMDGPUSubtarget.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/R600/AMDGPUSubtarget.h | 2 | ||||
| -rw-r--r-- | lib/Target/R600/Processors.td | 26 |
4 files changed, 33 insertions, 12 deletions
diff --git a/lib/Target/R600/AMDGPU.td b/lib/Target/R600/AMDGPU.td index 36c4156091..c4e5efc8d6 100644 --- a/lib/Target/R600/AMDGPU.td +++ b/lib/Target/R600/AMDGPU.td @@ -72,6 +72,16 @@ class SubtargetFeatureFetchLimit <string Value> : def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">; def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">; +class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature< + "wavefrontsize"#Value, + "WavefrontSize", + !cast<string>(Value), + "The number of threads per wavefront">; + +def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>; +def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>; +def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>; + class SubtargetFeatureGeneration <string Value, list<SubtargetFeature> Implies> : SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value, @@ -87,7 +97,7 @@ def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN", [FeatureFetchLimit16]>; def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS", - [FeatureFetchLimit16]>; + [FeatureFetchLimit16, FeatureWavefrontSize64]>; def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS", [Feature64BitPtr, FeatureFP64]>; diff --git a/lib/Target/R600/AMDGPUSubtarget.cpp b/lib/Target/R600/AMDGPUSubtarget.cpp index 51d9eadbaf..ed7742cdc2 100644 --- a/lib/Target/R600/AMDGPUSubtarget.cpp +++ b/lib/Target/R600/AMDGPUSubtarget.cpp @@ -38,6 +38,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : CaymanISA = false; EnableIRStructurizer = true; EnableIfCvt = true; + WavefrontSize = 0; ParseSubtargetFeatures(GPU, FS); DevName = GPU; } @@ -74,6 +75,10 @@ bool AMDGPUSubtarget::isIfCvtEnabled() const { return EnableIfCvt; } +unsigned +AMDGPUSubtarget::getWavefrontSize() const { + return WavefrontSize; +} bool AMDGPUSubtarget::isTargetELF() const { return false; diff --git a/lib/Target/R600/AMDGPUSubtarget.h b/lib/Target/R600/AMDGPUSubtarget.h index 060571e26b..53c7d2531a 100644 --- a/lib/Target/R600/AMDGPUSubtarget.h +++ b/lib/Target/R600/AMDGPUSubtarget.h @@ -51,6 +51,7 @@ private: bool CaymanISA; bool EnableIRStructurizer; bool EnableIfCvt; + unsigned WavefrontSize; InstrItineraryData InstrItins; @@ -68,6 +69,7 @@ public: bool hasCaymanISA() const; bool IsIRStructurizerEnabled() const; bool isIfCvtEnabled() const; + unsigned getWavefrontSize() const; virtual bool enableMachineScheduler() const { return getGeneration() <= NORTHERN_ISLANDS; diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td index 5499a20dfc..e601f35316 100644 --- a/lib/Target/R600/Processors.td +++ b/lib/Target/R600/Processors.td @@ -17,45 +17,49 @@ def : Proc<"", R600_VLIW5_Itin, [FeatureR600, FeatureVertexCache]>; def : Proc<"r600", R600_VLIW5_Itin, - [FeatureR600 , FeatureVertexCache]>; + [FeatureR600 , FeatureVertexCache, FeatureWavefrontSize64]>; + +def : Proc<"r630", R600_VLIW5_Itin, + [FeatureR600, FeatureVertexCache, FeatureWavefrontSize32]>; def : Proc<"rs880", R600_VLIW5_Itin, - [FeatureR600]>; + [FeatureR600, FeatureWavefrontSize16]>; def : Proc<"rv670", R600_VLIW5_Itin, - [FeatureR600, FeatureFP64, FeatureVertexCache]>; + [FeatureR600, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>; //===----------------------------------------------------------------------===// // R700 //===----------------------------------------------------------------------===// def : Proc<"rv710", R600_VLIW5_Itin, - [FeatureR700, FeatureVertexCache]>; + [FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>; def : Proc<"rv730", R600_VLIW5_Itin, - [FeatureR700, FeatureVertexCache]>; + [FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>; def : Proc<"rv770", R600_VLIW5_Itin, - [FeatureR700, FeatureFP64, FeatureVertexCache]>; + [FeatureR700, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>; //===----------------------------------------------------------------------===// // Evergreen //===----------------------------------------------------------------------===// def : Proc<"cedar", R600_VLIW5_Itin, - [FeatureEvergreen, FeatureVertexCache]>; + [FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize32]>; def : Proc<"redwood", R600_VLIW5_Itin, - [FeatureEvergreen, FeatureVertexCache]>; + [FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64]>; def : Proc<"sumo", R600_VLIW5_Itin, - [FeatureEvergreen]>; + [FeatureEvergreen, FeatureWavefrontSize64]>; def : Proc<"juniper", R600_VLIW5_Itin, - [FeatureEvergreen, FeatureVertexCache]>; + [FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64]>; def : Proc<"cypress", R600_VLIW5_Itin, - [FeatureEvergreen, FeatureFP64, FeatureVertexCache]>; + [FeatureEvergreen, FeatureFP64, FeatureVertexCache, + FeatureWavefrontSize64]>; //===----------------------------------------------------------------------===// // Northern Islands |