diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 21 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp | 22 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 11 | ||||
| -rw-r--r-- | test/CodeGen/X86/vec_split.ll | 29 |
4 files changed, 74 insertions, 9 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index b355cc9a64..2c0ed3f586 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4327,6 +4327,27 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) { } } + // Treat SETCC as a mask and promote the result type based on the targets + // expected SETCC result type. This will ensure that SETCC and VSELECT are + // both split by the type legalizer. This is done to prevent the type + // legalizer from unrolling SETCC into scalar comparions. + EVT SelectVT = N->getValueType(0); + if (N0.getOpcode() == ISD::SETCC && + N0.getValueType() != getSetCCResultType(SelectVT)) { + SDLoc MaskDL(N0); + EVT MaskVT = getSetCCResultType(SelectVT); + + SDValue Mask = DAG.getNode(ISD::SETCC, MaskDL, MaskVT, N0->getOperand(0), + N0->getOperand(1), N0->getOperand(2)); + + AddToWorkList(Mask.getNode()); + + SDValue LHS = N->getOperand(1); + SDValue RHS = N->getOperand(2); + + return DAG.getNode(ISD::VSELECT, DL, SelectVT, Mask, LHS, RHS); + } + return SDValue(); } diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp index d2c26d5507..136d104a4b 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp @@ -489,14 +489,20 @@ void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue &Lo, SDValue Cond = N->getOperand(0); CL = CH = Cond; if (Cond.getValueType().isVector()) { - assert(Cond.getValueType().getVectorElementType() == MVT::i1 && - "Condition legalized before result?"); - unsigned NumElements = Cond.getValueType().getVectorNumElements(); - EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements / 2); - CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond, - DAG.getConstant(0, TLI.getVectorIdxTy())); - CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond, - DAG.getConstant(NumElements / 2, TLI.getVectorIdxTy())); + if (Cond.getOpcode() == ISD::SETCC) { + assert(Cond.getValueType() == getSetCCResultType(N->getValueType(0)) && + "Condition has not been prepared for split!"); + GetSplitVector(Cond, CL, CH); + } else { + assert(Cond.getValueType().getVectorElementType() == MVT::i1 && + "Condition legalized before result?"); + unsigned NumElements = Cond.getValueType().getVectorNumElements(); + EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements / 2); + CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond, + DAG.getConstant(0, TLI.getVectorIdxTy())); + CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond, + DAG.getConstant(NumElements / 2, TLI.getVectorIdxTy())); + } } Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index b3cac0523f..974a1ee2da 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1535,7 +1535,16 @@ void X86TargetLowering::resetOperationActions() { } EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { - if (!VT.isVector()) return MVT::i8; + if (!VT.isVector()) + return MVT::i8; + + const TargetMachine &TM = getTargetMachine(); + if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) + switch(VT.getVectorNumElements()) { + case 8: return MVT::v8i1; + case 16: return MVT::v16i1; + } + return VT.changeVectorElementTypeToInteger(); } diff --git a/test/CodeGen/X86/vec_split.ll b/test/CodeGen/X86/vec_split.ll new file mode 100644 index 0000000000..a49af34f57 --- /dev/null +++ b/test/CodeGen/X86/vec_split.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=x86-64 -mcpu=corei7 < %s | FileCheck %s -check-prefix=SSE4 +; RUN: llc -march=x86-64 -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX2 + +define <16 x i16> @split16(<16 x i16> %a, <16 x i16> %b, <16 x i8> %__mask) { +; SSE4-LABEL: split16: +; SSE4: pminuw +; SSE4: pminuw +; AVX2-LABEL: split16: +; AVX2: vpminuw +; AVX2: ret + %1 = icmp ult <16 x i16> %a, %b + %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b + ret <16 x i16> %2 +} + +define <32 x i16> @split32(<32 x i16> %a, <32 x i16> %b, <32 x i8> %__mask) { +; SSE4-LABEL: split32: +; SSE4: pminuw +; SSE4: pminuw +; SSE4: pminuw +; SSE4: pminuw +; AVX2-LABEL: split32: +; AVX2: vpminuw +; AVX2: vpminuw +; AVX2: ret + %1 = icmp ult <32 x i16> %a, %b + %2 = select <32 x i1> %1, <32 x i16> %a, <32 x i16> %b + ret <32 x i16> %2 +} |