diff options
| -rw-r--r-- | lib/Target/X86/AsmParser/X86AsmParser.cpp | 27 | ||||
| -rw-r--r-- | test/MC/AsmParser/X86/x86_instructions.s | 25 |
2 files changed, 47 insertions, 5 deletions
diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index 5052931340..dde34631ef 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -923,6 +923,24 @@ ParseInstruction(StringRef Name, SMLoc NameLoc, std::swap(Operands[1], Operands[2]); } + // The assembler accepts these instructions with no operand as a synonym for + // an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)". + if ((Name == "fxch" || Name == "fucom" || Name == "fucomp" || + Name == "faddp" || Name == "fsubp" || Name == "fsubrp" || + Name == "fmulp" || Name == "fdivp" || Name == "fdivrp") && + Operands.size() == 1) { + Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"), + NameLoc, NameLoc)); + } + + // The assembler accepts these instructions with no operand as a synonym for + // an instruction acting on st,st(1). e.g. "faddp" -> "faddp %st(0),%st(1)". + //if (() && + // Operands.size() == 1) { + // Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"), + // NameLoc, NameLoc)); + //} + return false; } @@ -959,11 +977,10 @@ bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { } -bool -X86ATTAsmParser::MatchInstruction(SMLoc IDLoc, - const SmallVectorImpl<MCParsedAsmOperand*> - &Operands, - MCInst &Inst) { +bool X86ATTAsmParser:: +MatchInstruction(SMLoc IDLoc, + const SmallVectorImpl<MCParsedAsmOperand*> &Operands, + MCInst &Inst) { assert(!Operands.empty() && "Unexpect empty operand list!"); bool WasOriginallyInvalidOperand = false; diff --git a/test/MC/AsmParser/X86/x86_instructions.s b/test/MC/AsmParser/X86/x86_instructions.s index d4444f8952..4bdd171445 100644 --- a/test/MC/AsmParser/X86/x86_instructions.s +++ b/test/MC/AsmParser/X86/x86_instructions.s @@ -210,3 +210,28 @@ inl %dx out %al, (%dx) out %ax, (%dx) outl %eax, (%dx) + + +// rdar://8431422 + +// CHECK: fxch %st(1) +// CHECK: fucom %st(1) +// CHECK: fucomp %st(1) +// CHECK: faddp %st(1) +// CHECK: faddp %st(0) +// CHECK: fsubp %st(1) +// CHECK: fsubrp %st(1) +// CHECK: fmulp %st(1) +// CHECK: fdivp %st(1) +// CHECK: fdivrp %st(1) + +fxch +fucom +fucomp +faddp +faddp %st +fsubp +fsubrp +fmulp +fdivp +fdivrp |