diff options
21 files changed, 155 insertions, 573 deletions
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 8b0931ac61..7c0bed8479 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -17,7 +17,6 @@ #define LLVM_CODEGEN_MACHINEINSTR_H #include "llvm/CodeGen/MachineOperand.h" -#include "llvm/CodeGen/MemOperand.h" namespace llvm { @@ -36,7 +35,6 @@ class MachineInstr { // are determined at construction time). std::vector<MachineOperand> Operands; // the operands - std::vector<MemOperand> MemOperands; // information on memory references MachineInstr *Prev, *Next; // Links for MBB's intrusive list. MachineBasicBlock *Parent; // Pointer to the owning basic block. @@ -96,18 +94,6 @@ public: /// unsigned getNumExplicitOperands() const; - /// Access to memory operands of the instruction - unsigned getNumMemOperands() const { return MemOperands.size(); } - - const MemOperand& getMemOperand(unsigned i) const { - assert(i < getNumMemOperands() && "getMemOperand() out of range!"); - return MemOperands[i]; - } - MemOperand& getMemOperand(unsigned i) { - assert(i < getNumMemOperands() && "getMemOperand() out of range!"); - return MemOperands[i]; - } - /// isIdenticalTo - Return true if this instruction is identical to (same /// opcode and same operands as) the specified instruction. bool isIdenticalTo(const MachineInstr *Other) const { @@ -210,12 +196,6 @@ public: /// void RemoveOperand(unsigned i); - /// addMemOperand - Add a MemOperand to the machine instruction, referencing - /// arbitrary storage. - void addMemOperand(const MemOperand &MO) { - MemOperands.push_back(MO); - } - private: /// getRegInfo - If this instruction is embedded into a MachineFunction, /// return the MachineRegisterInfo object for the current function, otherwise diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h index 51900603ac..97d6736ac0 100644 --- a/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/include/llvm/CodeGen/MachineInstrBuilder.h @@ -83,12 +83,6 @@ public: MI->addOperand(MachineOperand::CreateES(FnName, 0)); return *this; } - - /// addMemOperand - Add a memory operand to the machine instruction. - const MachineInstrBuilder &addMemOperand(const MemOperand &MO) const { - MI->addMemOperand(MO); - return *this; - } }; /// BuildMI - Builder interface. Specify how to create the initial instruction diff --git a/include/llvm/CodeGen/MemOperand.h b/include/llvm/CodeGen/MemOperand.h index e9f05f3eed..e69de29bb2 100644 --- a/include/llvm/CodeGen/MemOperand.h +++ b/include/llvm/CodeGen/MemOperand.h @@ -1,82 +0,0 @@ -//===-- llvm/CodeGen/MemOperand.h - MemOperand class ------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the declaration of the MemOperand class, which is a -// description of a memory reference. It is used to help track dependencies -// in the backend. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CODEGEN_MEMOPERAND_H -#define LLVM_CODEGEN_MEMOPERAND_H - -namespace llvm { - -class Value; - -//===----------------------------------------------------------------------===// -/// MemOperand - A description of a memory reference used in the backend. -/// Instead of holding a StoreInst or LoadInst, this class holds the address -/// Value of the reference along with a byte size and offset. This allows it -/// to describe lowered loads and stores. Also, the special PseudoSourceValue -/// objects can be used to represent loads and stores to memory locations -/// that aren't explicit in the regular LLVM IR. -/// -class MemOperand { - const Value *V; - unsigned int Flags; - int Offset; - int Size; - unsigned int Alignment; - -public: - /// Flags values. These may be or'd together. - enum MemOperandFlags { - /// The memory access reads data. - MOLoad = 1, - /// The memory access writes data. - MOStore = 2, - /// The memory access is volatile. - MOVolatile = 4 - }; - - /// MemOperand - Construct an MemOperand object with the specified - /// address Value, flags, offset, size, and alignment. - MemOperand(const Value *v, unsigned int f, int o, int s, unsigned int a) - : V(v), Flags(f), Offset(o), Size(s), Alignment(a) {} - - /// getValue - Return the base address of the memory access. - /// Special values are PseudoSourceValue::FPRel, PseudoSourceValue::SPRel, - /// and the other PseudoSourceValue members which indicate references to - /// frame/stack pointer relative references and other special references. - const Value *getValue() const { return V; } - - /// getFlags - Return the raw flags of the source value, \see MemOperandFlags. - unsigned int getFlags() const { return Flags; } - - /// getOffset - For normal values, this is a byte offset added to the base - /// address. For PseudoSourceValue::FPRel values, this is the FrameIndex - /// number. - int getOffset() const { return Offset; } - - /// getSize - Return the size in bytes of the memory reference. - int getSize() const { return Size; } - - /// getAlignment - Return the minimum known alignment in bytes of the - /// memory reference. - unsigned int getAlignment() const { return Alignment; } - - bool isLoad() const { return Flags & MOLoad; } - bool isStore() const { return Flags & MOStore; } - bool isVolatile() const { return Flags & MOVolatile; } -}; - -} // End llvm namespace - -#endif diff --git a/include/llvm/CodeGen/PseudoSourceValue.h b/include/llvm/CodeGen/PseudoSourceValue.h index bae7e23173..e69de29bb2 100644 --- a/include/llvm/CodeGen/PseudoSourceValue.h +++ b/include/llvm/CodeGen/PseudoSourceValue.h @@ -1,62 +0,0 @@ -//===-- llvm/CodeGen/PseudoSourceValue.h ------------------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the declaration of the PseudoSourceValue class. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CODEGEN_PSEUDOSOURCEVALUE_H -#define LLVM_CODEGEN_PSEUDOSOURCEVALUE_H - -#include "llvm/Value.h" - -namespace llvm { - /// PseudoSourceValue - Special value supplied for machine level alias - /// analysis. It indicates that the a memory access references the functions - /// stack frame (e.g., a spill slot), below the stack frame (e.g., argument - /// space), or constant pool. - class PseudoSourceValue : public Value { - const char *name; - public: - explicit PseudoSourceValue(const char *_name); - - virtual void print(std::ostream &OS) const; - - /// classof - Methods for support type inquiry through isa, cast, and - /// dyn_cast: - /// - static inline bool classof(const PseudoSourceValue *) { return true; } - static inline bool classof(const Value *V) { - return V->getValueID() == PseudoSourceValueVal; - } - - /// A pseudo source value referencing to the stack frame of a function, - /// e.g., a spill slot. - static const PseudoSourceValue FPRel; - - /// A source value referencing the area below the stack frame of a function, - /// e.g., the argument space. - static const PseudoSourceValue SPRel; - - /// A source value referencing the global offset table (or something the - /// like). - static const PseudoSourceValue GPRel; - - /// A source value relative to some kind of thread id/pointer. - static const PseudoSourceValue TPRel; - - /// A SV referencing the constant pool - static const PseudoSourceValue CPRel; - - /// A SV referencing the jump table - static const PseudoSourceValue JTRel; - }; -} // End llvm namespace - -#endif diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index fdd5700357..77d1a1cce4 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -279,7 +279,6 @@ namespace llvm { if (isa<ConstantPoolSDNode>(Node)) return true; if (isa<JumpTableSDNode>(Node)) return true; if (isa<ExternalSymbolSDNode>(Node)) return true; - if (isa<MemOperandSDNode>(Node)) return true; return false; } @@ -313,15 +312,11 @@ namespace llvm { /// (which do not go into the machine instrs.) static unsigned CountResults(SDNode *Node); - /// CountOperands - The inputs to target nodes have any actual inputs first, - /// followed by optional memory operands chain operand, then flag operands. - /// Compute the number of actual operands that will go into the machine - /// instr. + /// CountOperands The inputs to target nodes have any actual inputs first, + /// followed by an optional chain operand, then flag operands. Compute the + /// number of actual operands that will go into the machine instr. static unsigned CountOperands(SDNode *Node); - /// CountMemOperands - Find the index of the last MemOperandSDNode - static unsigned CountMemOperands(SDNode *Node); - /// EmitNode - Generate machine code for an node and needed dependencies. /// VRBaseMap contains, for each already emitted node, the first virtual /// register number for the results of the node. @@ -362,8 +357,6 @@ namespace llvm { void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum, const TargetInstrDesc *II, DenseMap<SDOperand, unsigned> &VRBaseMap); - - void AddMemOperand(MachineInstr *MI, const MemOperand &MO); }; /// createBURRListDAGScheduler - This creates a bottom up register usage diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 9730112719..a9ad9a452d 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -381,12 +381,8 @@ public: SDOperand getIndexedStore(SDOperand OrigStoe, SDOperand Base, SDOperand Offset, ISD::MemIndexedMode AM); - // getSrcValue - Construct a node to track a Value* through the backend. - SDOperand getSrcValue(const Value *v); - - // getMemOperand - Construct a node to track a memory reference - // through the backend. - SDOperand getMemOperand(const MemOperand &MO); + // getSrcValue - construct a node to track a Value* through the backend + SDOperand getSrcValue(const Value* I, int offset = 0); /// UpdateNodeOperands - *Mutate* the specified node in-place to have the /// specified operands. If the resultant node already exists in the DAG, diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index cb4ac72d91..d0011c3347 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -25,7 +25,6 @@ #include "llvm/ADT/iterator" #include "llvm/ADT/APFloat.h" #include "llvm/CodeGen/ValueTypes.h" -#include "llvm/CodeGen/MemOperand.h" #include "llvm/Support/DataTypes.h" #include <cassert> @@ -537,15 +536,11 @@ namespace ISD { // pointer, and a SRCVALUE. VAEND, VASTART, - // SRCVALUE - This is a node type that holds a Value* that is used to - // make reference to a value in the LLVM IR. + // SRCVALUE - This corresponds to a Value*, and is used to associate memory + // locations with their value. This allows one use alias analysis + // information in the backend. SRCVALUE, - // MEMOPERAND - This is a node that contains a MemOperand which records - // information about a memory reference. This is used to make AliasAnalysis - // queries from the backend. - MEMOPERAND, - // PCMARKER - This corresponds to the pcmarker intrinsic. PCMARKER, @@ -1390,16 +1385,17 @@ public: class SrcValueSDNode : public SDNode { const Value *V; + int offset; virtual void ANCHOR(); // Out-of-line virtual method to give class a home. protected: friend class SelectionDAG; - /// Create a SrcValue for a general value. - explicit SrcValueSDNode(const Value *v) - : SDNode(ISD::SRCVALUE, getSDVTList(MVT::Other)), V(v) {} + SrcValueSDNode(const Value* v, int o) + : SDNode(ISD::SRCVALUE, getSDVTList(MVT::Other)), V(v), offset(o) { + } public: - /// getValue - return the contained Value. const Value *getValue() const { return V; } + int getOffset() const { return offset; } static bool classof(const SrcValueSDNode *) { return true; } static bool classof(const SDNode *N) { @@ -1408,29 +1404,6 @@ public: }; -/// MemOperandSDNode - An SDNode that holds a MemOperand. This is -/// used to represent a reference to memory after ISD::LOAD -/// and ISD::STORE have been lowered. -/// -class MemOperandSDNode : public SDNode { - virtual void ANCHOR(); // Out-of-line virtual method to give class a home. -protected: - friend class SelectionDAG; - /// Create a MemOperand node - explicit MemOperandSDNode(MemOperand mo) - : SDNode(ISD::MEMOPERAND, getSDVTList(MVT::Other)), MO(mo) {} - -public: - /// MO - The contained MemOperand. - const MemOperand MO; - - static bool classof(const MemOperandSDNode *) { return true; } - static bool classof(const SDNode *N) { - return N->getOpcode() == ISD::MEMOPERAND; - } -}; - - class RegisterSDNode : public SDNode { unsigned Reg; virtual void ANCHOR(); // Out-of-line virtual method to give class a home. @@ -1580,10 +1553,6 @@ public: /// isUnindexed - Return true if this is NOT a pre/post inc/dec load/store. bool isUnindexed() const { return AddrMode == ISD::UNINDEXED; } - /// getMemOperand - Return a MemOperand object describing the memory - /// reference performed by this load or store. - MemOperand getMemOperand() const; - static bool classof(const LSBaseSDNode *N) { return true; } static bool classof(const SDNode *N) { return N->getOpcode() == ISD::LOAD || diff --git a/include/llvm/Value.h b/include/llvm/Value.h index e1cc6f2697..fc1cf48209 100644 --- a/include/llvm/Value.h +++ b/include/llvm/Value.h @@ -188,7 +188,6 @@ public: ConstantPointerNullVal, // This is an instance of ConstantPointerNull InlineAsmVal, // This is an instance of InlineAsm InstructionVal, // This is an instance of Instruction - PseudoSourceValueVal, // This is an instance of PseudoSourceValue // Markers: ConstantFirstVal = FunctionVal, diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index f40ac91e74..e1e2336b50 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -15,8 +15,6 @@ #include "llvm/Value.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/PseudoSourceValue.h" -#include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrDesc.h" @@ -294,7 +292,6 @@ MachineInstr::MachineInstr(const MachineInstr &MI) { TID = &MI.getDesc(); NumImplicitOps = MI.NumImplicitOps; Operands.reserve(MI.getNumOperands()); - MemOperands = MI.MemOperands; // Add operands for (unsigned i = 0; i != MI.getNumOperands(); ++i) { @@ -630,34 +627,6 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { getOperand(i).print(OS, TM); } - if (getNumMemOperands() > 0) { - OS << ", SV:"; - for (unsigned i = 0; i < getNumMemOperands(); i++) { - const MemOperand &MRO = getMemOperand(i); - const Value *V = MRO.getValue(); - - assert(V && "SV missing."); - assert((MRO.isLoad() || MRO.isStore()) && - "SV has to be a load, store or both."); - - if (MRO.isVolatile()) - OS << "Volatile"; - if (MRO.isLoad()) - OS << "LD"; - if (MRO.isStore()) - OS << "ST"; - - OS << MRO.getSize(); - - if (!V->getName().empty()) - OS << "[" << V->getName() << " + " << MRO.getOffset() << "]"; - else if (isa<PseudoSourceValue>(V)) - OS << "[" << *V << " + " << MRO.getOffset() << "]"; - else - OS << "[" << V << " + " << MRO.getOffset() << "]"; - } - } - OS << "\n"; } diff --git a/lib/CodeGen/PseudoSourceValue.cpp b/lib/CodeGen/PseudoSourceValue.cpp index da9af49f94..e69de29bb2 100644 --- a/lib/CodeGen/PseudoSourceValue.cpp +++ b/lib/CodeGen/PseudoSourceValue.cpp @@ -1,33 +0,0 @@ -//===-- llvm/CodeGen/PseudoSourceValue.cpp ----------------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the PseudoSourceValue class. -// -//===----------------------------------------------------------------------===// - -#include "llvm/CodeGen/PseudoSourceValue.h" -#include "llvm/DerivedTypes.h" - -namespace llvm { - const PseudoSourceValue PseudoSourceValue::FPRel("FPRel"); - const PseudoSourceValue PseudoSourceValue::SPRel("SPRel"); - const PseudoSourceValue PseudoSourceValue::GPRel("GPRel"); - const PseudoSourceValue PseudoSourceValue::TPRel("TPRel"); - const PseudoSourceValue PseudoSourceValue::CPRel("CPRel"); - const PseudoSourceValue PseudoSourceValue::JTRel("JTRel"); - - PseudoSourceValue::PseudoSourceValue(const char *_name) : - Value(PointerType::getUnqual(Type::Int8Ty), PseudoSourceValueVal), - name(_name) { - } - - void PseudoSourceValue::print(std::ostream &OS) const { - OS << name; - } -} diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 9a4bec2acc..55634c91d0 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -16,7 +16,6 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetData.h" @@ -510,10 +509,9 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); if (Extend) { return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), - CPIdx, &PseudoSourceValue::CPRel, 0, MVT::f32); + CPIdx, NULL, 0, MVT::f32); } else { - return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::CPRel, 0); + return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); } } @@ -798,7 +796,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case ISD::TargetExternalSymbol: case ISD::VALUETYPE: case ISD::SRCVALUE: - case ISD::MEMOPERAND: case ISD::STRING: case ISD::CONDCODE: // Primitives must all be legal. @@ -1306,14 +1303,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { MVT::ValueType IdxVT = Tmp3.getValueType(); MVT::ValueType PtrVT = TLI.getPointerTy(); SDOperand StackPtr = DAG.CreateStackTemporary(VT); - - FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(StackPtr.Val); - assert(StackPtrFI); - int SPFI = StackPtrFI->getIndex(); - // Store the vector. - SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, - &PseudoSourceValue::FPRel, SPFI); + SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); // Truncate or zero extend offset to target pointer type. unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; @@ -1323,9 +1314,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); // Store the scalar value. - Ch = DAG.getStore(Ch, Tmp2, StackPtr2, &PseudoSourceValue::FPRel, SPFI); + Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); // Load the updated vector. - Result = DAG.getLoad(VT, Ch, StackPtr, &PseudoSourceValue::FPRel, SPFI); + Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); break; } } @@ -1674,10 +1665,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { SDOperand LD; switch (EntrySize) { default: assert(0 && "Size of jump table not supported yet."); break; - case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, - &PseudoSourceValue::JTRel, 0); break; - case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, - &PseudoSourceValue::JTRel, 0); break; + case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; + case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; } Addr = LD; @@ -3238,14 +3227,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } break; case TargetLowering::Expand: { - const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); - SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); + SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); + SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, + SV->getValue(), SV->getOffset()); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); + Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), + SV->getOffset()); // Load the actual argument out of the pointer VAList Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); Tmp1 = LegalizeOp(Result.getValue(1)); @@ -3281,10 +3272,12 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case TargetLowering::Expand: // This defaults to loading a pointer from the input and storing it to the // output, returning the chain. - const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); - const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); - Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0); - Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0); + SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); + SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); + Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), + SVD->getOffset()); + Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), + SVS->getOffset()); break; } break; @@ -4279,14 +4272,16 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); Result = TLI.CustomPromoteOperation(Tmp3, DAG); } else { - const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); - SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); + SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); + SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, + SV->getValue(), SV->getOffset()); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); + Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), + SV->getOffset()); // Load the actual argument out of the pointer VAList Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); } @@ -4742,10 +4737,6 @@ SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, // Create the stack frame object. SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); - FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(FIPtr); - assert(StackPtrFI); - int SPFI = StackPtrFI->getIndex(); - unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType()); unsigned SlotSize = MVT::getSizeInBits(SlotVT); unsigned DestSize = MVT::getSizeInBits(DestVT); @@ -4754,12 +4745,10 @@ SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, // later than DestVT. SDOperand Store; if (SrcSize > SlotSize) - Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, - &PseudoSourceValue::FPRel, SPFI, SlotVT); + Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0,SlotVT); else { assert(SrcSize == SlotSize && "Invalid store"); - Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, - &PseudoSourceValue::FPRel, SPFI, SlotVT); + Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); } // Result is a load from the stack slot. @@ -4774,15 +4763,9 @@ SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { // Create a vector sized/aligned stack slot, store the value to element #0, // then load the whole vector back out. SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); - - FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(StackPtr); - assert(StackPtrFI); - int SPFI = StackPtrFI->getIndex(); - SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, - &PseudoSourceValue::FPRel, SPFI); - return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, - &PseudoSourceValue::FPRel, SPFI); + NULL, 0); + return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); } @@ -4846,8 +4829,7 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { } Constant *CP = ConstantVector::get(CV); SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); - return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::CPRel, 0); + return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); } if (SplatValue.Val) { // Splat of one value? @@ -5189,13 +5171,11 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); SDOperand FudgeInReg; if (DestTy == MVT::f32) - FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::CPRel, 0); + FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) // FIXME: Avoid the extend by construction the right constantpool? FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), - CPIdx, &PseudoSourceValue::CPRel, 0, - MVT::f32); + CPIdx, NULL, 0, MVT::f32); else assert(0 && "Unexpected conversion"); @@ -5337,13 +5317,11 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); SDOperand FudgeInReg; if (DestVT == MVT::f32) - FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::CPRel, 0); + FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); else { FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::CPRel, 0, - MVT::f32)); + NULL, 0, MVT::f32)); } return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); @@ -6752,14 +6730,10 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, // Lower to a store/load so that it can be split. // FIXME: this could be improved probably. SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); - FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr.Val); - assert(FI && "Expecting CreateStackTemporary to return a frame index.\n"); SDOperand St = DAG.getStore(DAG.getEntryNode(), - InOp, Ptr, - &PseudoSourceValue::FPRel, FI->getIndex()); - InOp = DAG.getLoad(Op.getValueType(), St, Ptr, - &PseudoSourceValue::FPRel, FI->getIndex()); + InOp, Ptr, NULL, 0); + InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); } // Split the vector and convert each of the pieces now. SplitVectorOp(InOp, Lo, Hi); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 3873c33a20..aad1f87ed9 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -277,27 +277,15 @@ unsigned ScheduleDAG::CountResults(SDNode *Node) { return N; } -/// CountOperands - The inputs to target nodes have any actual inputs first, -/// followed by optional memory operands chain operand, then flag operands. -/// Compute the number of actual operands that will go into the machine istr. +/// CountOperands The inputs to target nodes have any actual inputs first, +/// followed by an optional chain operand, then flag operands. Compute the +/// number of actual operands that will go into the machine instr. unsigned ScheduleDAG::CountOperands(SDNode *Node) { unsigned N = Node->getNumOperands(); while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) --N; if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) --N; // Ignore chain if it exists. - while (N && MemOperandSDNode::classof(Node->getOperand(N - 1).Val)) - --N; // Ignore MemOperand nodes - return N; -} - -/// CountMemOperands - Find the index of the last MemOperandSDNode operand -unsigned ScheduleDAG::CountMemOperands(SDNode *Node) { - unsigned N = Node->getNumOperands(); - while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) - --N; - if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) - --N; // Ignore chain if it exists. return N; } @@ -529,10 +517,6 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, } -void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MemOperand &MO) { - MI->addMemOperand(MO); -} - // Returns the Register Class of a subregister static const TargetRegisterClass *getSubRegisterRegClass( const TargetRegisterClass *TRC, @@ -691,7 +675,6 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, unsigned NumResults = CountResults(Node); unsigned NodeOperands = CountOperands(Node); - unsigned NodeMemOperands = CountMemOperands(Node); unsigned NumMIOperands = NodeOperands + NumResults; bool HasPhysRegOuts = (NumResults > II.getNumDefs()) && II.getImplicitDefs() != 0; @@ -714,10 +697,6 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, for (unsigned i = 0; i != NodeOperands; ++i) AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap); - // Emit all of the memory operands of this instruction - for (unsigned i = NodeOperands; i != NodeMemOperands; ++i) - AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO); - // Commute node if it has been determined to be profitable. if (CommuteSet.count(Node)) { MachineInstr *NewMI = TII->commuteInstruction(MI); @@ -778,7 +757,6 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, case ISD::EntryToken: // fall thru case ISD::TokenFactor: case ISD::LABEL: - case ISD::SRCVALUE: break; case ISD::CopyToReg: { unsigned InReg; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 28d7006ac9..6f0e98d825 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -20,7 +20,6 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Support/MathExtras.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetData.h" @@ -359,16 +358,10 @@ static void AddNodeIDNode(FoldingSetNodeID &ID, SDNode *N) { case ISD::Register: ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); break; - case ISD::SRCVALUE: - ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); - break; - case ISD::MEMOPERAND: { - const MemOperand &MO = cast<MemOperandSDNode>(N)->MO; - ID.AddPointer(MO.getValue()); - ID.AddInteger(MO.getFlags()); - ID.AddInteger(MO.getOffset()); - ID.AddInteger(MO.getSize()); - ID.AddInteger(MO.getAlignment()); + case ISD::SRCVALUE: { + SrcValueSDNode *SV = cast<SrcValueSDNode>(N); + ID.AddPointer(SV->getValue()); + ID.AddInteger(SV->getOffset()); break; } case ISD::FrameIndex: @@ -939,42 +932,18 @@ SDOperand SelectionDAG::getRegister(unsigned RegNo, MVT::ValueType VT) { return SDOperand(N, 0); } -SDOperand SelectionDAG::getSrcValue(const Value *V) { +SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { assert((!V || isa<PointerType>(V->getType())) && "SrcValue is not a pointer?"); FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); ID.AddPointer(V); - - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDOperand(E, 0); - - SDNode *N = new SrcValueSDNode(V); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDOperand(N, 0); -} - -SDOperand SelectionDAG::getMemOperand(const MemOperand &MO) { - const Value *v = MO.getValue(); - assert((!v || isa<PointerType>(v->getType())) && - "SrcValue is not a pointer?"); - - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); - ID.AddPointer(v); - ID.AddInteger(MO.getFlags()); - ID.AddInteger(MO.getOffset()); - ID.AddInteger(MO.getSize()); - ID.AddInteger(MO.getAlignment()); - + ID.AddInteger(Offset); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDOperand(E, 0); - - SDNode *N = new MemOperandSDNode(MO); + SDNode *N = new SrcValueSDNode(V, Offset); CSEMap.InsertNode(N, IP); AllNodes.push_back(N); return SDOperand(N, 0); @@ -3464,7 +3433,6 @@ void JumpTableSDNode::ANCHOR() {} void ConstantPoolSDNode::ANCHOR() {} void BasicBlockSDNode::ANCHOR() {} void SrcValueSDNode::ANCHOR() {} -void MemOperandSDNode::ANCHOR() {} void RegisterSDNode::ANCHOR() {} void ExternalSymbolSDNode::ANCHOR() {} void CondCodeSDNode::ANCHOR() {} @@ -3489,26 +3457,6 @@ GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, TheGlobal = const_cast<GlobalValue*>(GA); } -/// getMemOperand - Return a MemOperand object describing the memory -/// reference performed by this load or store. -MemOperand LSBaseSDNode::getMemOperand() const { - int Size = (MVT::getSizeInBits(getMemoryVT()) + 7) >> 3; - int Flags = - getOpcode() == ISD::LOAD ? MemOperand::MOLoad : MemOperand::MOStore; - if (IsVolatile) Flags |= MemOperand::MOVolatile; - - // Check if the load references a frame index, and does not have - // an SV attached. - const FrameIndexSDNode *FI = - dyn_cast<const FrameIndexSDNode>(getBasePtr().Val); - if (!getSrcValue() && FI) - return MemOperand(&PseudoSourceValue::FPRel, Flags, - FI->getIndex(), Size, Alignment); - else - return MemOperand(getSrcValue(), Flags, - getSrcValueOffset(), Size, Alignment); -} - /// Profile - Gather unique data for the node. /// void SDNode::Profile(FoldingSetNodeID &ID) { @@ -3701,7 +3649,6 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::PCMARKER: return "PCMarker"; case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; case ISD::SRCVALUE: return "SrcValue"; - case ISD::MEMOPERAND: return "MemOperand"; case ISD::EntryToken: return "EntryToken"; case ISD::TokenFactor: return "TokenFactor"; case ISD::AssertSext: return "AssertSext"; @@ -4006,14 +3953,9 @@ void SDNode::dump(const SelectionDAG *G) const { cerr << "'" << ES->getSymbol() << "'"; } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { if (M->getValue()) - cerr << "<" << M->getValue() << ">"; - else - cerr << "<null>"; - } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { - if (M->MO.getValue()) - cerr << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; + cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; else - cerr << "<null:" << M->MO.getOffset() << ">"; + cerr << "<null:" << M->getOffset() << ">"; } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { cerr << ":" << MVT::getValueTypeString(N->getVT()); } else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp index 719b949591..95c791b43e 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp @@ -142,14 +142,9 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node, Op += "'" + std::string(ES->getSymbol()) + "'"; } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(Node)) { if (M->getValue()) - Op += "<" + M->getValue()->getName() + ">"; + Op += "<" + M->getValue()->getName() + ":" + itostr(M->getOffset()) + ">"; else - Op += "<null>"; - } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(Node)) { - if (M->MO.getValue()) - Op += "<" + M->MO.getValue()->getName() + ":" + itostr(M->MO.getOffset()) + ">"; - else - Op += "<null:" + itostr(M->MO.getOffset()) + ">"; + Op += "<null:" + itostr(M->getOffset()) + ">"; } else if (const VTSDNode *N = dyn_cast<VTSDNode>(Node)) { Op = Op + " VT=" + MVT::getValueTypeString(N->getVT()); } else if (const StringSDNode *N = dyn_cast<StringSDNode>(Node)) { diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 65df5e8273..dfe3bec9a5 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -911,8 +911,9 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, // memory location argument. MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); - const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); + SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); + return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), + SV->getOffset()); } static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index d20e1f7fb1..c359a5bcdb 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -491,9 +491,10 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::VAARG: { SDOperand Chain = Op.getOperand(0); SDOperand VAListP = Op.getOperand(1); - const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); + SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2)); - SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0); + SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS->getValue(), + VAListS->getOffset()); SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), @@ -526,11 +527,13 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { SDOperand Chain = Op.getOperand(0); SDOperand DestP = Op.getOperand(1); SDOperand SrcP = Op.getOperand(2); - const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); - const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); + SrcValueSDNode *DestS = cast<SrcValueSDNode>(Op.getOperand(3)); + SrcValueSDNode *SrcS = cast<SrcValueSDNode>(Op.getOperand(4)); - SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0); - SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0); + SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, + SrcS->getValue(), SrcS->getOffset()); + SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS->getValue(), + DestS->getOffset()); SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, DAG.getConstant(8, MVT::i64)); Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32); @@ -541,11 +544,12 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::VASTART: { SDOperand Chain = Op.getOperand(0); SDOperand VAListP = Op.getOperand(1); - const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); + SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2)); // vastart stores the address of the VarArgsBase and VarArgsOffset SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64); - SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0); + SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS->getValue(), + VAListS->getOffset()); SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64), diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index ef772749ed..d81d5e6686 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -581,16 +581,16 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { } case ISD::VAARG: { MVT::ValueType VT = getPointerTy(); - const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); + SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), - SV, 0); + SV->getValue(), SV->getOffset()); // Increment the pointer, VAList, to the next vaarg SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, VT)); // Store the incremented VAList to the legalized pointer VAIncr = DAG.getStore(VAList.getValue(1), VAIncr, - Op.getOperand(1), SV, 0); + Op.getOperand(1), SV->getValue(), SV->getOffset()); // Load the actual argument out of the pointer VAList return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0); } @@ -598,8 +598,9 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64); - const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); + SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); + return DAG.getStore(Op.getOperand(0), FR, + Op.getOperand(1), SV->getValue(), SV->getOffset()); } // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: break; diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 30f5f1fea9..79fc16bfca 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -24,7 +24,6 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/Constants.h" #include "llvm/Function.h" @@ -1173,8 +1172,9 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, // memory location argument. MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); - const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); + SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); + return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), + SV->getOffset()); } // For ELF 32 ABI we follow the layout of the va_list struct. @@ -1208,41 +1208,37 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); + SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); - uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8; - SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); - - uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1; - SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); - - uint64_t FPROffset = 1; - SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); + SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, + PtrVT); + SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1, + PtrVT); + SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT); - const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); + SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); // Store first byte : number of int regs SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, - Op.getOperand(1), SV, 0); - uint64_t nextOffset = FPROffset; + Op.getOperand(1), SV->getValue(), + SV->getOffset()); SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), ConstFPROffset); // Store second byte : number of float regs - SDOperand secondStore = - DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset); - nextOffset += StackOffset; + SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr, + SV->getValue(), SV->getOffset()); nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); // Store second word : arguments given on stack - SDOperand thirdStore = - DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset); - nextOffset += FrameOffset; + SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr, + SV->getValue(), SV->getOffset()); nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); // Store third word : arguments given in registers - return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset); + return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(), + SV->getOffset()); } @@ -2200,11 +2196,9 @@ static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { Op.getOperand(0)); // STD the extended value into the stack slot. - MemOperand MO(&PseudoSourceValue::FPRel, - MemOperand::MOStore, FrameIdx, 8, 8); SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, DAG.getEntryNode(), Ext64, FIdx, - DAG.getMemOperand(MO)); + DAG.getSrcValue(NULL)); // Load the value as a double. SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); @@ -3303,11 +3297,11 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, std::vector<MVT::ValueType> VTs; VTs.push_back(MVT::i32); VTs.push_back(MVT::Other); - SDOperand MO = DAG.getMemOperand(LD->getMemOperand()); + SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); SDOperand Ops[] = { LD->getChain(), // Chain LD->getBasePtr(), // Ptr - MO, // MemOperand + SV, // SrcValue DAG.getValueType(N->getValueType(0)) // VT }; SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 6c5b79daa7..f8dfbe3efa 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -804,23 +804,25 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, DAG.getRegister(SP::I6, MVT::i32), DAG.getConstant(VarArgsFrameOffset, MVT::i32)); - const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0); + SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); + return DAG.getStore(Op.getOperand(0), Offset, + Op.getOperand(1), SV->getValue(), SV->getOffset()); } case ISD::VAARG: { SDNode *Node = Op.Val; MVT::ValueType VT = Node->getValueType(0); SDOperand InChain = Node->getOperand(0); SDOperand VAListPtr = Node->getOperand(1); - const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); - SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, SV, 0); + SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); + SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, + SV->getValue(), SV->getOffset()); // Increment the pointer, VAList, to the next vaarg SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, getPointerTy())); // Store the incremented VAList to the legalized pointer InChain = DAG.getStore(VAList.getValue(1), NextPtr, - VAListPtr, SV, 0); + VAListPtr, SV->getValue(), SV->getOffset()); // Load the actual argument out of the pointer VAList, unless this is an // f64 load. if (VT != MVT::f64) { diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 873a587ded..b19456e1fd 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -31,7 +31,6 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Debug.h" @@ -1089,8 +1088,7 @@ SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG, SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); if (isByVal) return FIN; - return DAG.getLoad(VA.getValVT(), Root, FIN, - &PseudoSourceValue::FPRel, FI); + return DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0); } SDOperand @@ -1218,9 +1216,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], X86::GR64RegisterClass); SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); - SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, - &PseudoSourceValue::FPRel, - RegSaveFrameIndex); + SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8)); @@ -1233,9 +1229,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass); SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); - SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, - &PseudoSourceValue::FPRel, - RegSaveFrameIndex); + SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(16)); @@ -1564,8 +1558,7 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { Flags, DAG)); } else { // Store relative to framepointer. - MemOpChains2.push_back(DAG.getStore(Chain, Source, FIN, - &PseudoSourceValue::FPRel, FI)); + MemOpChains2.push_back(DAG.getStore(Chain, Source, FIN, NULL, 0)); } } } @@ -3791,8 +3784,7 @@ X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { // the GV offset field. Platform check is inside GVRequiresExtraLoad() call // The same applies for external symbols during PIC codegen if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false)) - Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, - &PseudoSourceValue::GPRel, 0); + Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0); return Result; } @@ -3850,8 +3842,7 @@ LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA); if (GA->getGlobal()->isDeclaration()) // initial exec TLS model - Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, - &PseudoSourceValue::TPRel, 0); + Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, NULL, 0); // The address of the thread local variable is the add of the thread // pointer with the offset of the variable. @@ -3983,7 +3974,7 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), - StackSlot, &PseudoSourceValue::FPRel, SSFI); + StackSlot, NULL, 0); // These are really Legal; caller falls through into that case. if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) @@ -4024,8 +4015,7 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { Ops.push_back(DAG.getValueType(Op.getValueType())); Ops.push_back(InFlag); Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); - Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, - &PseudoSourceValue::FPRel, SSFI); + Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0); } return Result; @@ -4063,8 +4053,7 @@ FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) { SDOperand Value = Op.getOperand(0); if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); - Chain = DAG.getStore(Chain, Value, StackSlot, - &PseudoSourceValue::FPRel, SSFI); + Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0); SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); SDOperand Ops[] = { Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) @@ -4123,8 +4112,7 @@ SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) { } Constant *C = ConstantVector::get(CV); SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::CPRel, 0, + SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0, false, 16); return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); } @@ -4152,8 +4140,7 @@ SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) { } Constant *C = ConstantVector::get(CV); SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::CPRel, 0, + SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0, false, 16); if (MVT::isVector(VT)) { return DAG.getNode(ISD::BIT_CONVERT, VT, @@ -4201,8 +4188,7 @@ SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { } Constant *C = ConstantVector::get(CV); SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::CPRel, 0, + SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, NULL, 0, false, 16); SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); @@ -4230,8 +4216,7 @@ SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { } C = ConstantVector::get(CV); CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::CPRel, 0, + SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0, false, 16); SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); @@ -4687,13 +4672,14 @@ SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){ } SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) { - const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); + SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); if (!Subtarget->is64Bit()) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); - return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(), + SV->getOffset()); } // __va_list_tag: @@ -4706,26 +4692,28 @@ SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) { // Store gp_offset SDOperand Store = DAG.getStore(Op.getOperand(0), DAG.getConstant(VarArgsGPOffset, MVT::i32), - FIN, SV, 0); + FIN, SV->getValue(), SV->getOffset()); MemOps.push_back(Store); // Store fp_offset FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); Store = DAG.getStore(Op.getOperand(0), DAG.getConstant(VarArgsFPOffset, MVT::i32), - FIN, SV, 0); + FIN, SV->getValue(), SV->getOffset()); MemOps.push_back(Store); // Store ptr to overflow_arg_area FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); - Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0); + Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(), + SV->getOffset()); MemOps.push_back(Store); // Store ptr to reg_save_area. FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8)); SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); - Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0); + Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(), + SV->getOffset()); MemOps.push_back(Store); return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size()); } @@ -4735,15 +4723,18 @@ SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) { SDOperand Chain = Op.getOperand(0); SDOperand DstPtr = Op.getOperand(1); SDOperand SrcPtr = Op.getOperand(2); - const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); - const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); + SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3)); + SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4)); - SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr, SrcSV, 0); + SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr, + SrcSV->getValue(), SrcSV->getOffset()); Chain = SrcPtr.getValue(1); for (unsigned i = 0; i < 3; ++i) { - SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr, SrcSV, 0); + SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr, + SrcSV->getValue(), SrcSV->getOffset()); Chain = Val.getValue(1); - Chain = DAG.getStore(Chain, Val, DstPtr, DstSV, 0); + Chain = DAG.getStore(Chain, Val, DstPtr, + DstSV->getValue(), DstSV->getOffset()); if (i == 2) break; SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr, @@ -4923,7 +4914,7 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, SDOperand FPtr = Op.getOperand(2); // nested function SDOperand Nest = Op.getOperand(3); // 'nest' parameter value - const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); + SrcValueSDNode *TrmpSV = cast<SrcValueSDNode>(Op.getOperand(4)); const X86InstrInfo *TII = ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); @@ -4947,31 +4938,33 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 SDOperand Addr = Trmp; OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, - TrmpAddr, 0); + TrmpSV->getValue(), TrmpSV->getOffset()); Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64)); - OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2); + OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpSV->getValue(), + TrmpSV->getOffset() + 2, false, 2); // Load the 'nest' parameter value into R10. // R10 is specified in X86CallingConv.td OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64)); OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, - TrmpAddr, 10); + TrmpSV->getValue(), TrmpSV->getOffset() + 10); Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64)); - OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2); + OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(), + TrmpSV->getOffset() + 12, false, 2); // Jump to the nested function. OpCode = (JMP64r << 8) | REX_WB; // jmpq *... Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64)); OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, - TrmpAddr, 20); + TrmpSV->getValue(), TrmpSV->getOffset() + 20); unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64)); OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr, - TrmpAddr, 22); + TrmpSV->getValue(), TrmpSV->getOffset() + 22); SDOperand Ops[] = { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) }; @@ -5029,18 +5022,20 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, const unsigned char N86Reg = ((X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg); OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8), - Trmp, TrmpAddr, 0); + Trmp, TrmpSV->getValue(), TrmpSV->getOffset()); Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32)); - OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1); + OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(), + TrmpSV->getOffset() + 1, false, 1); const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32)); OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr, - TrmpAddr, 5, false, 1); + TrmpSV->getValue() + 5, TrmpSV->getOffset()); Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32)); - OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1); + OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpSV->getValue(), + TrmpSV->getOffset() + 6, false, 1); SDOperand Ops[] = { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) }; diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index 05c27c47d9..ae62c9fcb2 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -311,12 +311,6 @@ private: std::vector<std::pair<std::string, std::string> > OrigChains; std::set<std::string> Duplicates; - /// LSI - Load/Store information. - /// Save loads/stores matched by a pattern, and generate a MemOperandSDNode - /// for each memory access. This facilitates the use of AliasAnalysis in - /// the backend. - std::vector<std::string> LSI; - /// GeneratedCode - This is the buffer that we emit code to. The first int /// indicates whether this is an exit predicate (something that should be /// tested, and if true, the match fails) [when 1], or normal code to emit @@ -377,15 +371,6 @@ public: void EmitMatchCode(TreePatternNode *N, TreePatternNode *P, const std::string &RootName, const std::string &ChainSuffix, bool &FoundChain) { - - // Save loads/stores matched by a pattern. - if (!N->isLeaf() && N->getName().empty() && - ((N->getOperator()->getName() == "ld") || - (N->getOperator()->getName() == "st") || - (N->getOperator()->getName() == "ist"))) { - LSI.push_back(RootName); - } - bool isRoot = (P == NULL); // Emit instruction predicates. Each predicate is just a string for now. if (isRoot) { @@ -948,18 +933,6 @@ public: } } - // Generate MemOperandSDNodes nodes for each memory accesses covered by this - // pattern. - if (isRoot) { - std::vector<std::string>::const_iterator mi, mie; - for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) { - emitCode("SDOperand LSI_" + *mi + " = " - "CurDAG->getMemOperand(cast<LSBaseSDNode>(" + - *mi + ")->getMemOperand());"); - AllOps.push_back("LSI_" + *mi); - } - } - // Emit all the chain and CopyToReg stuff. bool ChainEmitted = NodeHasChain; if (NodeHasChain) |