diff options
74 files changed, 641 insertions, 314 deletions
diff --git a/autoconf/configure.ac b/autoconf/configure.ac index 3c3ddaa666..4a5fc66fdf 100644 --- a/autoconf/configure.ac +++ b/autoconf/configure.ac @@ -659,6 +659,7 @@ for a_target in $TARGETS_TO_BUILD; do LLVM_NATIVE_TARGET="LLVMInitialize${LLVM_NATIVE_ARCH}Target" LLVM_NATIVE_TARGETINFO="LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo" LLVM_NATIVE_MCASMINFO="LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo" + LLVM_NATIVE_MCCODEGENINFO="LLVMInitialize${LLVM_NATIVE_ARCH}MCCodeGenInfo" LLVM_NATIVE_ASMPRINTER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter" if test -f ${srcdir}/lib/Target/${LLVM_NATIVE_ARCH}/AsmParser/Makefile ; then LLVM_NATIVE_ASMPARSER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmParser" @@ -669,6 +670,8 @@ for a_target in $TARGETS_TO_BUILD; do [LLVM name for the native TargetInfo init function, if available]) AC_DEFINE_UNQUOTED(LLVM_NATIVE_MCASMINFO, $LLVM_NATIVE_MCASMINFO, [LLVM name for the native MCAsmInfo init function, if available]) + AC_DEFINE_UNQUOTED(LLVM_NATIVE_MCCODEGENINFO, $LLVM_NATIVE_MCCODEGENINFO, + [LLVM name for the native MCCodeGenInfo init function, if available]) AC_DEFINE_UNQUOTED(LLVM_NATIVE_ASMPRINTER, $LLVM_NATIVE_ASMPRINTER, [LLVM name for the native AsmPrinter init function, if available]) if test -f ${srcdir}/lib/Target/${LLVM_NATIVE_ARCH}/AsmParser/Makefile ; then diff --git a/cmake/config-ix.cmake b/cmake/config-ix.cmake index 46f33de8d7..c4e753a25b 100755 --- a/cmake/config-ix.cmake +++ b/cmake/config-ix.cmake @@ -337,6 +337,7 @@ else () set(LLVM_NATIVE_TARGET LLVMInitialize${LLVM_NATIVE_ARCH}Target) set(LLVM_NATIVE_TARGETINFO LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo) set(LLVM_NATIVE_MCASMINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo) + set(LLVM_NATIVE_MCCODEGENINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCCODEGENInfo) set(LLVM_NATIVE_ASMPRINTER LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter) endif () @@ -5121,6 +5121,7 @@ _ACEOF LLVM_NATIVE_TARGET="LLVMInitialize${LLVM_NATIVE_ARCH}Target" LLVM_NATIVE_TARGETINFO="LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo" LLVM_NATIVE_MCASMINFO="LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo" + LLVM_NATIVE_MCCODEGENINFO="LLVMInitialize${LLVM_NATIVE_ARCH}MCCodeGenInfo" LLVM_NATIVE_ASMPRINTER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter" if test -f ${srcdir}/lib/Target/${LLVM_NATIVE_ARCH}/AsmParser/Makefile ; then LLVM_NATIVE_ASMPARSER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmParser" @@ -5142,6 +5143,11 @@ _ACEOF cat >>confdefs.h <<_ACEOF +#define LLVM_NATIVE_MCCODEGENINFO $LLVM_NATIVE_MCCODEGENINFO +_ACEOF + + +cat >>confdefs.h <<_ACEOF #define LLVM_NATIVE_ASMPRINTER $LLVM_NATIVE_ASMPRINTER _ACEOF diff --git a/include/llvm-c/Target.h b/include/llvm-c/Target.h index d21644011a..fbaf0d55f2 100644 --- a/include/llvm-c/Target.h +++ b/include/llvm-c/Target.h @@ -46,6 +46,11 @@ typedef struct LLVMStructLayout *LLVMStructLayoutRef; #include "llvm/Config/Targets.def" #undef LLVM_TARGET /* Explicit undef to make SWIG happier */ +#define LLVM_TARGET(TargetName) \ + void LLVMInitialize##TargetName##MCCodeGenInfo(void); +#include "llvm/Config/Targets.def" +#undef LLVM_TARGET /* Explicit undef to make SWIG happier */ + /** LLVMInitializeAllTargetInfos - The main program should call this function if it wants access to all available targets that LLVM is configured to support. */ @@ -73,6 +78,7 @@ static inline LLVMBool LLVMInitializeNativeTarget(void) { LLVM_NATIVE_TARGETINFO(); LLVM_NATIVE_TARGET(); LLVM_NATIVE_MCASMINFO(); + LLVM_NATIVE_MCCODEGENINFO(); return 0; #else return 1; diff --git a/include/llvm/Config/config.h.cmake b/include/llvm/Config/config.h.cmake index 0b8a0add7e..82ebc56415 100644 --- a/include/llvm/Config/config.h.cmake +++ b/include/llvm/Config/config.h.cmake @@ -560,6 +560,9 @@ /* LLVM name for the native MCAsmInfo init function, if available */ #cmakedefine LLVM_NATIVE_MCASMINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo +/* LLVM name for the native MCCodeGenInfo init function, if available */ +#cmakedefine LLVM_NATIVE_MCCODEGENINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCCodeGenInfo + /* Define if this is Unixish platform */ #cmakedefine LLVM_ON_UNIX ${LLVM_ON_UNIX} diff --git a/include/llvm/Config/config.h.in b/include/llvm/Config/config.h.in index 0a716ea797..6042d93107 100644 --- a/include/llvm/Config/config.h.in +++ b/include/llvm/Config/config.h.in @@ -576,6 +576,9 @@ /* LLVM name for the native MCAsmInfo init function, if available */ #undef LLVM_NATIVE_MCASMINFO +/* LLVM name for the native MCCODEGENInfo init function, if available */ +#undef LLVM_NATIVE_MCCODEGENINFO + /* LLVM name for the native Target init function, if available */ #undef LLVM_NATIVE_TARGET diff --git a/include/llvm/Config/llvm-config.h.cmake b/include/llvm/Config/llvm-config.h.cmake index 5f948a2ab1..63d2b3f94d 100644 --- a/include/llvm/Config/llvm-config.h.cmake +++ b/include/llvm/Config/llvm-config.h.cmake @@ -61,6 +61,9 @@ /* LLVM name for the native MCAsmInfo init function, if available */ #cmakedefine LLVM_NATIVE_MCASMINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo +/* LLVM name for the native MCCodeGenInfo init function, if available */ +#cmakedefine LLVM_NATIVE_MCCODEGENINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCCodeGenInfo + /* LLVM name for the native AsmPrinter init function, if available */ #cmakedefine LLVM_NATIVE_ASMPRINTER LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter diff --git a/include/llvm/Config/llvm-config.h.in b/include/llvm/Config/llvm-config.h.in index bc8ddce56f..980096a3aa 100644 --- a/include/llvm/Config/llvm-config.h.in +++ b/include/llvm/Config/llvm-config.h.in @@ -61,6 +61,9 @@ /* LLVM name for the native MCAsmInfo init function, if available */ #undef LLVM_NATIVE_MCASMINFO +/* LLVM name for the native MCCodeGenInfo init function, if available */ +#undef LLVM_NATIVE_MCCODEGENINFO + /* LLVM name for the native AsmPrinter init function, if available */ #undef LLVM_NATIVE_ASMPRINTER diff --git a/include/llvm/ExecutionEngine/ExecutionEngine.h b/include/llvm/ExecutionEngine/ExecutionEngine.h index f66f9eca03..2afa7913f4 100644 --- a/include/llvm/ExecutionEngine/ExecutionEngine.h +++ b/include/llvm/ExecutionEngine/ExecutionEngine.h @@ -18,6 +18,7 @@ #include <vector> #include <map> #include <string> +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/ValueMap.h" @@ -201,6 +202,7 @@ public: CodeGenOpt::Level OptLevel = CodeGenOpt::Default, bool GVsWithCode = true, + Reloc::Model RM = Reloc::Default, CodeModel::Model CMM = CodeModel::Default); @@ -463,6 +465,7 @@ private: CodeGenOpt::Level OptLevel; JITMemoryManager *JMM; bool AllocateGVsWithCode; + Reloc::Model RelocModel; CodeModel::Model CMModel; std::string MArch; std::string MCPU; @@ -476,6 +479,7 @@ private: OptLevel = CodeGenOpt::Default; JMM = NULL; AllocateGVsWithCode = false; + RelocModel = Reloc::Default; CMModel = CodeModel::Default; UseMCJIT = false; } @@ -517,6 +521,13 @@ public: return *this; } + /// setRelocationModel - Set the relocation model that the ExecutionEngine + /// target is using. Defaults to target specific default "Reloc::Default". + EngineBuilder &setRelocationModel(Reloc::Model RM) { + RelocModel = RM; + return *this; + } + /// setCodeModel - Set the CodeModel that the ExecutionEngine target /// data is using. Defaults to target specific default "CodeModel::Default". EngineBuilder &setCodeModel(CodeModel::Model M) { @@ -569,6 +580,7 @@ public: StringRef MArch, StringRef MCPU, const SmallVectorImpl<std::string>& MAttrs, + Reloc::Model RM, std::string *Err); ExecutionEngine *create(); diff --git a/include/llvm/MC/MCCodeGenInfo.h b/include/llvm/MC/MCCodeGenInfo.h new file mode 100644 index 0000000000..908922a253 --- /dev/null +++ b/include/llvm/MC/MCCodeGenInfo.h @@ -0,0 +1,36 @@ +//===-- llvm/MC/MCCodeGenInfo.h - Target CodeGen Info -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file tracks information about the target which can affect codegen, +// asm parsing, and asm printing. For example, relocation model. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCCODEGENINFO_H +#define LLVM_MC_MCCODEGENINFO_H + +namespace llvm { + // Relocation model types. + namespace Reloc { + enum Model { Default, Static, PIC_, DynamicNoPIC }; + } + + class MCCodeGenInfo { + /// RelocationModel - Relocation model: statcic, pic, etc. + /// + Reloc::Model RelocationModel; + + public: + void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default); + + Reloc::Model getRelocationModel() const { return RelocationModel; } + }; +} // namespace llvm + +#endif diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index ac41a58ccd..f4c845ab27 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -14,6 +14,7 @@ #ifndef LLVM_TARGET_TARGETMACHINE_H #define LLVM_TARGET_TARGETMACHINE_H +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/ADT/StringRef.h" #include <cassert> #include <string> @@ -23,6 +24,7 @@ namespace llvm { class InstrItineraryData; class JITCodeEmitter; class MCAsmInfo; +class MCCodeGenInfo; class MCContext; class Pass; class PassManager; @@ -41,16 +43,6 @@ class TargetSubtargetInfo; class formatted_raw_ostream; class raw_ostream; -// Relocation model types. -namespace Reloc { - enum Model { - Default, - Static, - PIC_, // Cannot be named PIC due to collision with -DPIC - DynamicNoPIC - }; -} - // Code model types. namespace CodeModel { enum Model { @@ -108,6 +100,10 @@ protected: // Can only create subclasses. std::string TargetCPU; std::string TargetFS; + /// CodeGenInfo - Low level target information such as relocation model. + /// + const MCCodeGenInfo *CodeGenInfo; + /// AsmInfo - Contains target specific asm information. /// const MCAsmInfo *AsmInfo; @@ -214,11 +210,7 @@ public: /// getRelocationModel - Returns the code generation relocation model. The /// choices are static, PIC, and dynamic-no-pic, and target default. - static Reloc::Model getRelocationModel(); - - /// setRelocationModel - Sets the code generation relocation model. - /// - static void setRelocationModel(Reloc::Model Model); + Reloc::Model getRelocationModel() const; /// getCodeModel - Returns the code model. The choices are small, kernel, /// medium, large, and target default. @@ -309,7 +301,7 @@ public: class LLVMTargetMachine : public TargetMachine { protected: // Can only create subclasses. LLVMTargetMachine(const Target &T, StringRef TargetTriple, - StringRef CPU, StringRef FS); + StringRef CPU, StringRef FS, Reloc::Model RM); private: /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for diff --git a/include/llvm/Target/TargetRegistry.h b/include/llvm/Target/TargetRegistry.h index a33d17ba57..7d63d56a84 100644 --- a/include/llvm/Target/TargetRegistry.h +++ b/include/llvm/Target/TargetRegistry.h @@ -19,6 +19,7 @@ #ifndef LLVM_TARGET_TARGETREGISTRY_H #define LLVM_TARGET_TARGETREGISTRY_H +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/ADT/Triple.h" #include <string> #include <cassert> @@ -37,6 +38,7 @@ namespace llvm { class MCRegisterInfo; class MCStreamer; class MCSubtargetInfo; + class MCCodeGenInfo; class TargetAsmBackend; class TargetAsmLexer; class TargetAsmParser; @@ -68,15 +70,17 @@ namespace llvm { typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T, StringRef TT); + typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT, Reloc::Model M); typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT); typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, StringRef CPU, StringRef Features); typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &Features); + StringRef TT, + StringRef CPU, + StringRef Features, + Reloc::Model RM); typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM, MCStreamer &Streamer); typedef TargetAsmBackend *(*AsmBackendCtorTy)(const Target &T, @@ -132,6 +136,10 @@ namespace llvm { /// registered. MCAsmInfoCtorFnTy MCAsmInfoCtorFn; + /// MCCodeGenInfoCtorFn - Constructor function for this target's MCCodeGenInfo, + /// if registered. + MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn; + /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo, /// if registered. MCInstrInfoCtorFnTy MCInstrInfoCtorFn; @@ -253,6 +261,14 @@ namespace llvm { return MCAsmInfoCtorFn(*this, Triple); } + /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation. + /// + MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model M) const { + if (!MCCodeGenInfoCtorFn) + return 0; + return MCCodeGenInfoCtorFn(Triple, M); + } + /// createMCInstrInfo - Create a MCInstrInfo implementation. /// MCInstrInfo *createMCInstrInfo() const { @@ -292,12 +308,12 @@ namespace llvm { /// feature set; it should always be provided. Generally this should be /// either the target triple from the module, or the target triple of the /// host if that does not exist. - TargetMachine *createTargetMachine(const std::string &Triple, - const std::string &CPU, - const std::string &Features) const { + TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU, + StringRef Features, + Reloc::Model RM = Reloc::Default) const { if (!TargetMachineCtorFn) return 0; - return TargetMachineCtorFn(*this, Triple, CPU, Features); + return TargetMachineCtorFn(*this, Triple, CPU, Features, RM); } /// createAsmBackend - Create a target specific assembly parser. @@ -500,6 +516,22 @@ namespace llvm { T.MCAsmInfoCtorFn = Fn; } + /// RegisterMCCodeGenInfo - Register a MCCodeGenInfo implementation for the + /// given target. + /// + /// Clients are responsible for ensuring that registration doesn't occur + /// while another thread is attempting to access the registry. Typically + /// this is done by initializing all targets at program startup. + /// + /// @param T - The target being registered. + /// @param Fn - A function to construct a MCCodeGenInfo for the target. + static void RegisterMCCodeGenInfo(Target &T, + Target::MCCodeGenInfoCtorFnTy Fn) { + // Ignore duplicate registration. + if (!T.MCCodeGenInfoCtorFn) + T.MCCodeGenInfoCtorFn = Fn; + } + /// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the /// given target. /// @@ -756,6 +788,39 @@ namespace llvm { } }; + /// RegisterMCCodeGenInfo - Helper template for registering a target codegen info + /// implementation. This invokes the static "Create" method on the class + /// to actually do the construction. Usage: + /// + /// extern "C" void LLVMInitializeFooTarget() { + /// extern Target TheFooTarget; + /// RegisterMCCodeGenInfo<FooMCCodeGenInfo> X(TheFooTarget); + /// } + template<class MCCodeGenInfoImpl> + struct RegisterMCCodeGenInfo { + RegisterMCCodeGenInfo(Target &T) { + TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator); + } + private: + static MCCodeGenInfo *Allocator(StringRef TT, Reloc::Model M) { + return new MCCodeGenInfoImpl(); + } + }; + + /// RegisterMCCodeGenInfoFn - Helper template for registering a target codegen + /// info implementation. This invokes the specified function to do the + /// construction. Usage: + /// + /// extern "C" void LLVMInitializeFooTarget() { + /// extern Target TheFooTarget; + /// RegisterMCCodeGenInfoFn X(TheFooTarget, TheFunction); + /// } + struct RegisterMCCodeGenInfoFn { + RegisterMCCodeGenInfoFn(Target &T, Target::MCCodeGenInfoCtorFnTy Fn) { + TargetRegistry::RegisterMCCodeGenInfo(T, Fn); + } + }; + /// RegisterMCInstrInfo - Helper template for registering a target instruction /// info implementation. This invokes the static "Create" method on the class /// to actually do the construction. Usage: @@ -871,10 +936,10 @@ namespace llvm { } private: - static TargetMachine *Allocator(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) { - return new TargetMachineImpl(T, TT, CPU, FS); + static TargetMachine *Allocator(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) { + return new TargetMachineImpl(T, TT, CPU, FS, RM); } }; diff --git a/include/llvm/Target/TargetSelect.h b/include/llvm/Target/TargetSelect.h index 3cccaa80b0..81fd9c94dc 100644 --- a/include/llvm/Target/TargetSelect.h +++ b/include/llvm/Target/TargetSelect.h @@ -31,6 +31,10 @@ extern "C" { #include "llvm/Config/Targets.def" #define LLVM_TARGET(TargetName) \ + void LLVMInitialize##TargetName##MCCodeGenInfo(); +#include "llvm/Config/Targets.def" + +#define LLVM_TARGET(TargetName) \ void LLVMInitialize##TargetName##MCInstrInfo(); #include "llvm/Config/Targets.def" @@ -91,6 +95,16 @@ namespace llvm { #include "llvm/Config/Targets.def" } + /// InitializeAllMCCodeGenInfos - The main program should call this function + /// if it wants access to all targets machines that LLVM is configured to + /// support, to make them available via the TargetRegistry. + /// + /// It is legal for a client to make multiple calls to this function. + inline void InitializeAllMCCodeGenInfos() { +#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCCodeGenInfo(); +#include "llvm/Config/Targets.def" + } + /// InitializeAllMCInstrInfos - The main program should call this function /// if it wants access to all available instruction infos for targets that /// LLVM is configured to support, to make them available via the @@ -164,6 +178,7 @@ namespace llvm { LLVM_NATIVE_TARGETINFO(); LLVM_NATIVE_TARGET(); LLVM_NATIVE_MCASMINFO(); + LLVM_NATIVE_MCCODEGENINFO(); return false; #else return true; diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index f14ee832c3..f36836237e 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -103,8 +103,10 @@ EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \"fast\" instruction selector")); LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, - StringRef CPU, StringRef FS) + StringRef CPU, StringRef FS, + Reloc::Model RM) : TargetMachine(T, Triple, CPU, FS) { + CodeGenInfo = T.createMCCodeGenInfo(Triple, RM); AsmInfo = T.createMCAsmInfo(Triple); } diff --git a/lib/ExecutionEngine/ExecutionEngine.cpp b/lib/ExecutionEngine/ExecutionEngine.cpp index dee8ea8a97..4995fa99cd 100644 --- a/lib/ExecutionEngine/ExecutionEngine.cpp +++ b/lib/ExecutionEngine/ExecutionEngine.cpp @@ -422,6 +422,7 @@ ExecutionEngine *ExecutionEngine::createJIT(Module *M, JITMemoryManager *JMM, CodeGenOpt::Level OptLevel, bool GVsWithCode, + Reloc::Model RM, CodeModel::Model CMM) { if (ExecutionEngine::JITCtor == 0) { if (ErrorStr) @@ -436,7 +437,7 @@ ExecutionEngine *ExecutionEngine::createJIT(Module *M, SmallVector<std::string, 1> MAttrs; TargetMachine *TM = - EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, ErrorStr); + EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, RM, ErrorStr); if (!TM || (ErrorStr && ErrorStr->length() > 0)) return 0; TM->setCodeModel(CMM); @@ -465,8 +466,8 @@ ExecutionEngine *EngineBuilder::create() { // Unless the interpreter was explicitly selected or the JIT is not linked, // try making a JIT. if (WhichEngine & EngineKind::JIT) { - if (TargetMachine *TM = - EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, ErrorStr)) { + if (TargetMachine *TM = EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, + RelocModel, ErrorStr)) { TM->setCodeModel(CMModel); if (UseMCJIT && ExecutionEngine::MCJITCtor) { diff --git a/lib/ExecutionEngine/JIT/JIT.h b/lib/ExecutionEngine/JIT/JIT.h index b879fc36e5..b50ec5f54f 100644 --- a/lib/ExecutionEngine/JIT/JIT.h +++ b/lib/ExecutionEngine/JIT/JIT.h @@ -100,9 +100,10 @@ public: CodeGenOpt::Level OptLevel = CodeGenOpt::Default, bool GVsWithCode = true, + Reloc::Model RM = Reloc::Default, CodeModel::Model CMM = CodeModel::Default) { return ExecutionEngine::createJIT(M, Err, JMM, OptLevel, GVsWithCode, - CMM); + RM, CMM); } virtual void addModule(Module *M); diff --git a/lib/ExecutionEngine/TargetSelect.cpp b/lib/ExecutionEngine/TargetSelect.cpp index f51aff3603..32dcf9e22e 100644 --- a/lib/ExecutionEngine/TargetSelect.cpp +++ b/lib/ExecutionEngine/TargetSelect.cpp @@ -30,6 +30,7 @@ TargetMachine *EngineBuilder::selectTarget(Module *Mod, StringRef MArch, StringRef MCPU, const SmallVectorImpl<std::string>& MAttrs, + Reloc::Model RM, std::string *ErrorStr) { Triple TheTriple(Mod->getTargetTriple()); if (TheTriple.getTriple().empty()) @@ -83,8 +84,8 @@ TargetMachine *EngineBuilder::selectTarget(Module *Mod, } // Allocate a target... - TargetMachine *Target = - TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU, FeaturesStr); + TargetMachine *Target = TheTarget->createTargetMachine(TheTriple.getTriple(), + MCPU, FeaturesStr, RM); assert(Target && "Could not allocate target machine!"); return Target; } diff --git a/lib/MC/CMakeLists.txt b/lib/MC/CMakeLists.txt index 22afa7e91c..64625bee31 100644 --- a/lib/MC/CMakeLists.txt +++ b/lib/MC/CMakeLists.txt @@ -6,6 +6,7 @@ add_llvm_library(LLVMMC MCAsmStreamer.cpp MCAssembler.cpp MCCodeEmitter.cpp + MCCodeGenInfo.cpp MCContext.cpp MCDisassembler.cpp MCELF.cpp diff --git a/lib/MC/MCCodeGenInfo.cpp b/lib/MC/MCCodeGenInfo.cpp new file mode 100644 index 0000000000..553cd9710d --- /dev/null +++ b/lib/MC/MCCodeGenInfo.cpp @@ -0,0 +1,20 @@ +//===-- MCCodeGenInfo.cpp - Target CodeGen Info -----------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file tracks information about the target which can affect codegen, +// asm parsing, and asm printing. For example, relocation model. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCCodeGenInfo.h" +using namespace llvm; + +void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM) { + RelocationModel = RM; +} diff --git a/lib/MC/MCDisassembler/Disassembler.cpp b/lib/MC/MCDisassembler/Disassembler.cpp index 19d7349bbd..2004bae848 100644 --- a/lib/MC/MCDisassembler/Disassembler.cpp +++ b/lib/MC/MCDisassembler/Disassembler.cpp @@ -41,6 +41,7 @@ LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo, // FIXME: We shouldn't need to initialize the Target(Machine)s. llvm::InitializeAllTargets(); llvm::InitializeAllMCAsmInfos(); + llvm::InitializeAllMCCodeGenInfos(); llvm::InitializeAllMCRegisterInfos(); llvm::InitializeAllAsmPrinters(); llvm::InitializeAllAsmParsers(); diff --git a/lib/MC/MCDisassembler/EDDisassembler.cpp b/lib/MC/MCDisassembler/EDDisassembler.cpp index 5448b5c6b2..cae54164ed 100644 --- a/lib/MC/MCDisassembler/EDDisassembler.cpp +++ b/lib/MC/MCDisassembler/EDDisassembler.cpp @@ -108,6 +108,7 @@ void EDDisassembler::initialize() { InitializeAllTargetInfos(); InitializeAllTargets(); + InitializeAllMCCodeGenInfos(); InitializeAllMCAsmInfos(); InitializeAllMCRegisterInfos(); InitializeAllMCSubtargetInfos(); diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index f0b176ad69..92f2f5bf40 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -62,25 +62,22 @@ extern "C" void LLVMInitializeARMTarget() { /// TargetMachine ctor - Create an ARM architecture model. /// -ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), +ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS), JITInfo(), InstrItins(Subtarget.getInstrItineraryData()) { - DefRelocModel = getRelocationModel(); - // Default to soft float ABI if (FloatABIType == FloatABI::Default) FloatABIType = FloatABI::Soft; } -ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : ARMBaseTargetMachine(T, TT, CPU, FS), InstrInfo(Subtarget), +ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : ARMBaseTargetMachine(T, TT, CPU, FS, RM), InstrInfo(Subtarget), DataLayout(Subtarget.isAPCS_ABI() ? std::string("e-p:32:32-f64:32:64-i64:32:64-" "v128:32:128-v64:32:64-n32") : @@ -95,10 +92,10 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT, "support ARM mode execution!"); } -ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : ARMBaseTargetMachine(T, TT, CPU, FS), +ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : ARMBaseTargetMachine(T, TT, CPU, FS, RM), InstrInfo(Subtarget.hasThumb2() ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), @@ -179,10 +176,6 @@ bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, JITCodeEmitter &JCE) { - // FIXME: Move this to TargetJITInfo! - if (DefRelocModel == Reloc::Default) - setRelocationModel(Reloc::Static); - // Machine code emitter pass for ARM. PM.add(createARMJITCodeEmitterPass(*this, JCE)); return false; diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h index bc3d46a50e..616ea9c3d2 100644 --- a/lib/Target/ARM/ARMTargetMachine.h +++ b/lib/Target/ARM/ARMTargetMachine.h @@ -37,11 +37,10 @@ protected: private: ARMJITInfo JITInfo; InstrItineraryData InstrItins; - Reloc::Model DefRelocModel; // Reloc model before it's overridden. public: - ARMBaseTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + ARMBaseTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual ARMJITInfo *getJITInfo() { return &JITInfo; } virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; } @@ -69,8 +68,8 @@ class ARMTargetMachine : public ARMBaseTargetMachine { ARMSelectionDAGInfo TSInfo; ARMFrameLowering FrameLowering; public: - ARMTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + ARMTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const ARMRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); @@ -108,8 +107,8 @@ class ThumbTargetMachine : public ARMBaseTargetMachine { // Either Thumb1FrameLowering or ARMFrameLowering. OwningPtr<ARMFrameLowering> FrameLowering; public: - ThumbTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + ThumbTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo virtual const ARMBaseRegisterInfo *getRegisterInfo() const { diff --git a/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp b/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp index d9a5fa223b..ebebcdc32c 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp @@ -15,7 +15,7 @@ #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/Target/TargetAsmLexer.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetMachine.h" // FIXME #include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/OwningPtr.h" diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index 510f4ab65f..6d6bee2179 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -142,3 +142,17 @@ extern "C" void LLVMInitializeARMMCAsmInfo() { RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo); RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo); } + +MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + if (RM == Reloc::Default) + RM = Reloc::DynamicNoPIC; + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeARMMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo); + TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo); +} + diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp index 3b65d41be8..4cdd3ab483 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.cpp +++ b/lib/Target/Alpha/AlphaTargetMachine.cpp @@ -22,19 +22,17 @@ extern "C" void LLVMInitializeAlphaTarget() { RegisterTargetMachine<AlphaTargetMachine> X(TheAlphaTarget); } -AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), +AlphaTargetMachine::AlphaTargetMachine(const Target &T, StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), DataLayout("e-f128:128:128-n64"), FrameLowering(Subtarget), Subtarget(TT, CPU, FS), TLInfo(*this), TSInfo(*this) { - setRelocationModel(Reloc::PIC_); } - //===----------------------------------------------------------------------===// // Pass Pipeline Configuration //===----------------------------------------------------------------------===// diff --git a/lib/Target/Alpha/AlphaTargetMachine.h b/lib/Target/Alpha/AlphaTargetMachine.h index cf00e5875d..1d930d0a5c 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.h +++ b/lib/Target/Alpha/AlphaTargetMachine.h @@ -36,8 +36,8 @@ class AlphaTargetMachine : public LLVMTargetMachine { AlphaSelectionDAGInfo TSInfo; public: - AlphaTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + AlphaTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { diff --git a/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp b/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp index 691b1aa89b..04bc434862 100644 --- a/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp +++ b/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp @@ -65,3 +65,15 @@ extern "C" void LLVMInitializeAlphaMCSubtargetInfo() { extern "C" void LLVMInitializeAlphaMCAsmInfo() { RegisterMCAsmInfo<AlphaMCAsmInfo> X(TheAlphaTarget); } + +MCCodeGenInfo *createAlphaMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + X->InitMCCodeGenInfo(Reloc::PIC_); + return X; +} + +extern "C" void LLVMInitializeAlphaMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheAlphaTarget, + createAlphaMCCodeGenInfo); +} + diff --git a/lib/Target/Blackfin/BlackfinTargetMachine.cpp b/lib/Target/Blackfin/BlackfinTargetMachine.cpp index a1c9f1c05e..0a474cdb68 100644 --- a/lib/Target/Blackfin/BlackfinTargetMachine.cpp +++ b/lib/Target/Blackfin/BlackfinTargetMachine.cpp @@ -22,10 +22,10 @@ extern "C" void LLVMInitializeBlackfinTarget() { } BlackfinTargetMachine::BlackfinTargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), + StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), DataLayout("e-p:32:32-i64:32-f64:32-n32"), Subtarget(TT, CPU, FS), TLInfo(*this), diff --git a/lib/Target/Blackfin/BlackfinTargetMachine.h b/lib/Target/Blackfin/BlackfinTargetMachine.h index bd7dc84f04..afe3919257 100644 --- a/lib/Target/Blackfin/BlackfinTargetMachine.h +++ b/lib/Target/Blackfin/BlackfinTargetMachine.h @@ -35,8 +35,8 @@ namespace llvm { BlackfinFrameLowering FrameLowering; BlackfinIntrinsicInfo IntrinsicInfo; public: - BlackfinTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + BlackfinTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const BlackfinInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { diff --git a/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp b/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp index 57fd7236c6..b4e89c1bbd 100644 --- a/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp +++ b/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp @@ -68,3 +68,14 @@ extern "C" void LLVMInitializeBlackfinMCSubtargetInfo() { extern "C" void LLVMInitializeBlackfinMCAsmInfo() { RegisterMCAsmInfo<BlackfinMCAsmInfo> X(TheBlackfinTarget); } + +MCCodeGenInfo *createBlackfinMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeBlackfinMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheBlackfinTarget, + createBlackfinMCCodeGenInfo); +} diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp index d6c278517b..4ff8f84891 100644 --- a/lib/Target/CBackend/CBackend.cpp +++ b/lib/Target/CBackend/CBackend.cpp @@ -71,6 +71,8 @@ extern "C" void LLVMInitializeCBackendMCInstrInfo() {} extern "C" void LLVMInitializeCBackendMCSubtargetInfo() {} +extern "C" void LLVMInitializeCBackendMCCodeGenInfo() {} + namespace { class CBEMCAsmInfo : public MCAsmInfo { public: diff --git a/lib/Target/CBackend/CTargetMachine.h b/lib/Target/CBackend/CTargetMachine.h index e64216be0b..e0af30de9a 100644 --- a/lib/Target/CBackend/CTargetMachine.h +++ b/lib/Target/CBackend/CTargetMachine.h @@ -20,8 +20,8 @@ namespace llvm { struct CTargetMachine : public TargetMachine { - CTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS) + CTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM) : TargetMachine(T, TT, CPU, FS) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, diff --git a/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp b/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp index 3c4147bc9f..a951f28219 100644 --- a/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp +++ b/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp @@ -77,3 +77,16 @@ static MCAsmInfo *createSPUMCAsmInfo(const Target &T, StringRef TT) { extern "C" void LLVMInitializeCellSPUMCAsmInfo() { RegisterMCAsmInfoFn X(TheCellSPUTarget, createSPUMCAsmInfo); } + +MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + // For the time being, use static relocations, since there's really no + // support for PIC yet. + X->InitMCCodeGenInfo(Reloc::Static); + return X; +} + +extern "C" void LLVMInitializeCellSPUMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheCellSPUTarget, + createSPUMCCodeGenInfo); +} diff --git a/lib/Target/CellSPU/SPUTargetMachine.cpp b/lib/Target/CellSPU/SPUTargetMachine.cpp index 3542a2b87e..8eabe9209d 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.cpp +++ b/lib/Target/CellSPU/SPUTargetMachine.cpp @@ -31,9 +31,9 @@ SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const { return &LR[0]; } -SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU,const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), +SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT, + StringRef CPU,StringRef FS, Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), @@ -41,9 +41,6 @@ SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT, TLInfo(*this), TSInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { - // For the time being, use static relocations, since there's really no - // support for PIC yet. - setRelocationModel(Reloc::Static); } //===----------------------------------------------------------------------===// diff --git a/lib/Target/CellSPU/SPUTargetMachine.h b/lib/Target/CellSPU/SPUTargetMachine.h index d96f86dcae..b48a517f82 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.h +++ b/lib/Target/CellSPU/SPUTargetMachine.h @@ -38,8 +38,8 @@ class SPUTargetMachine : public LLVMTargetMachine { SPUSelectionDAGInfo TSInfo; InstrItineraryData InstrItins; public: - SPUTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + SPUTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); /// Return the subtarget implementation object virtual const SPUSubtarget *getSubtargetImpl() const { diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp index 98ec22c75b..ad33cfa319 100644 --- a/lib/Target/CppBackend/CPPBackend.cpp +++ b/lib/Target/CppBackend/CPPBackend.cpp @@ -85,6 +85,8 @@ extern "C" void LLVMInitializeCppBackendMCInstrInfo() {} extern "C" void LLVMInitializeCppBackendMCSubtargetInfo() {} +extern "C" void LLVMInitializeCppBackendMCCodeGenInfo() {} + namespace { typedef std::vector<Type*> TypeList; typedef std::map<Type*,std::string> TypeMap; diff --git a/lib/Target/CppBackend/CPPTargetMachine.h b/lib/Target/CppBackend/CPPTargetMachine.h index 7322e3e34f..56f479502d 100644 --- a/lib/Target/CppBackend/CPPTargetMachine.h +++ b/lib/Target/CppBackend/CPPTargetMachine.h @@ -22,8 +22,8 @@ namespace llvm { class formatted_raw_ostream; struct CPPTargetMachine : public TargetMachine { - CPPTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS) + CPPTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM) : TargetMachine(T, TT, CPU, FS) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, diff --git a/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp b/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp index 1596596445..ac8caa2677 100644 --- a/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp +++ b/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp @@ -19,7 +19,7 @@ #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/Target/TargetAsmLexer.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetMachine.h" // FIXME #include "llvm/Target/TargetRegistry.h" #include <string> diff --git a/lib/Target/MBlaze/MBlazeTargetMachine.cpp b/lib/Target/MBlaze/MBlazeTargetMachine.cpp index 7208874aef..945c847ae9 100644 --- a/lib/Target/MBlaze/MBlazeTargetMachine.cpp +++ b/lib/Target/MBlaze/MBlazeTargetMachine.cpp @@ -67,19 +67,15 @@ extern "C" void LLVMInitializeMBlazeTarget() { // offset from the stack/frame pointer, using StackGrowsUp enables // an easier handling. MBlazeTargetMachine:: -MBlazeTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS): - LLVMTargetMachine(T, TT, CPU, FS), +MBlazeTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM): + LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS), DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"), InstrInfo(*this), FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { - if (getRelocationModel() == Reloc::Default) { - setRelocationModel(Reloc::Static); - } - if (getCodeModel() == CodeModel::Default) setCodeModel(CodeModel::Small); } diff --git a/lib/Target/MBlaze/MBlazeTargetMachine.h b/lib/Target/MBlaze/MBlazeTargetMachine.h index cd6caafbf3..6f32d1439a 100644 --- a/lib/Target/MBlaze/MBlazeTargetMachine.h +++ b/lib/Target/MBlaze/MBlazeTargetMachine.h @@ -41,8 +41,8 @@ namespace llvm { InstrItineraryData InstrItins; public: - MBlazeTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + MBlazeTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const MBlazeInstrInfo *getInstrInfo() const { return &InstrInfo; } diff --git a/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp b/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp index 9fb7820846..22ce1cb8b6 100644 --- a/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp +++ b/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp @@ -74,3 +74,16 @@ static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) { extern "C" void LLVMInitializeMBlazeMCAsmInfo() { RegisterMCAsmInfoFn X(TheMBlazeTarget, createMCAsmInfo); } + +MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + if (RM == Reloc::Default) + RM = Reloc::Static; + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeMBlazeMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheMBlazeTarget, + createMBlazeMCCodeGenInfo); +} diff --git a/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp b/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp index 3a356744bc..6aa62206ef 100644 --- a/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp +++ b/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -66,3 +66,14 @@ extern "C" void LLVMInitializeMSP430MCSubtargetInfo() { extern "C" void LLVMInitializeMSP430MCAsmInfo() { RegisterMCAsmInfo<MSP430MCAsmInfo> X(TheMSP430Target); } + +MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeMSP430MCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheMSP430Target, + createMSP430MCCodeGenInfo); +} diff --git a/lib/Target/MSP430/MSP430TargetMachine.cpp b/lib/Target/MSP430/MSP430TargetMachine.cpp index 971f512141..85ca533005 100644 --- a/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -25,10 +25,10 @@ extern "C" void LLVMInitializeMSP430Target() { } MSP430TargetMachine::MSP430TargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), + StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS), // FIXME: Check TargetData string. DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"), diff --git a/lib/Target/MSP430/MSP430TargetMachine.h b/lib/Target/MSP430/MSP430TargetMachine.h index 2a9eea0bcd..384176c1ed 100644 --- a/lib/Target/MSP430/MSP430TargetMachine.h +++ b/lib/Target/MSP430/MSP430TargetMachine.h @@ -38,8 +38,8 @@ class MSP430TargetMachine : public LLVMTargetMachine { MSP430FrameLowering FrameLowering; public: - MSP430TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + MSP430TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const TargetFrameLowering *getFrameLowering() const { return &FrameLowering; diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp index 3a2ed8a762..b83a69d06a 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -77,3 +77,24 @@ extern "C" void LLVMInitializeMipsMCAsmInfo() { RegisterMCAsmInfoFn X(TheMipsTarget, createMipsMCAsmInfo); RegisterMCAsmInfoFn Y(TheMipselTarget, createMipsMCAsmInfo); } + +MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + if (RM == Reloc::Default) { + // Abicall enables PIC by default + if (TT.find("mipsallegrex") != std::string::npos || + TT.find("psp") != std::string::npos) + RM = Reloc::Static; + else + RM = Reloc::PIC_; + } + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeMipsMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheMipsTarget, + createMipsMCCodeGenInfo); + TargetRegistry::RegisterMCCodeGenInfo(TheMipselTarget, + createMipsMCCodeGenInfo); +} diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index 20b9f4ea38..a195a48961 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -31,10 +31,10 @@ extern "C" void LLVMInitializeMipsTarget() { // an easier handling. // Using CodeModel::Large enables different CALL behavior. MipsTargetMachine:: -MipsTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, +MipsTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM, bool isLittle=false): - LLVMTargetMachine(T, TT, CPU, FS), + LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS, isLittle), DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : @@ -42,19 +42,12 @@ MipsTargetMachine(const Target &T, const std::string &TT, InstrInfo(*this), FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this) { - // Abicall enables PIC by default - if (getRelocationModel() == Reloc::Default) { - if (Subtarget.isABI_O32()) - setRelocationModel(Reloc::PIC_); - else - setRelocationModel(Reloc::Static); - } } MipselTargetMachine:: -MipselTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS) : - MipsTargetMachine(T, TT, CPU, FS, true) {} +MipselTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM) : + MipsTargetMachine(T, TT, CPU, FS, RM, true) {} // Install an instruction selector pass using // the ISelDag to gen Mips code. diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h index a021af2ff1..c1671e69bb 100644 --- a/lib/Target/Mips/MipsTargetMachine.h +++ b/lib/Target/Mips/MipsTargetMachine.h @@ -34,9 +34,9 @@ namespace llvm { MipsTargetLowering TLInfo; MipsSelectionDAGInfo TSInfo; public: - MipsTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, - bool isLittle); + MipsTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool isLittle); virtual const MipsInstrInfo *getInstrInfo() const { return &InstrInfo; } @@ -73,8 +73,8 @@ namespace llvm { /// class MipselTargetMachine : public MipsTargetMachine { public: - MipselTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + MipselTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; } // End llvm namespace diff --git a/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp b/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp index 065e698e9b..19d0c6dfa4 100644 --- a/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp +++ b/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp @@ -70,3 +70,14 @@ extern "C" void LLVMInitializePTXMCAsmInfo() { RegisterMCAsmInfo<PTXMCAsmInfo> X(ThePTX32Target); RegisterMCAsmInfo<PTXMCAsmInfo> Y(ThePTX64Target); } + +MCCodeGenInfo *createPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializePTXMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(ThePTX32Target, createPTXMCCodeGenInfo); + TargetRegistry::RegisterMCCodeGenInfo(ThePTX64Target, createPTXMCCodeGenInfo); +} diff --git a/lib/Target/PTX/PTXTargetMachine.cpp b/lib/Target/PTX/PTXTargetMachine.cpp index ab926e02d6..2d73599e8d 100644 --- a/lib/Target/PTX/PTXTargetMachine.cpp +++ b/lib/Target/PTX/PTXTargetMachine.cpp @@ -47,11 +47,11 @@ namespace { // DataLayout and FrameLowering are filled with dummy data PTXTargetMachine::PTXTargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS, - bool is64Bit) - : LLVMTargetMachine(T, TT, CPU, FS), + StringRef TT, + StringRef CPU, + StringRef FS, + Reloc::Model RM, bool is64Bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM), DataLayout(is64Bit ? DataLayout64 : DataLayout32), Subtarget(TT, CPU, FS, is64Bit), FrameLowering(Subtarget), @@ -59,18 +59,16 @@ PTXTargetMachine::PTXTargetMachine(const Target &T, TLInfo(*this) { } -PTX32TargetMachine::PTX32TargetMachine(const Target &T, - const std::string& TT, - const std::string& CPU, - const std::string& FS) - : PTXTargetMachine(T, TT, CPU, FS, false) { +PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : PTXTargetMachine(T, TT, CPU, FS, RM, false) { } -PTX64TargetMachine::PTX64TargetMachine(const Target &T, - const std::string& TT, - const std::string& CPU, - const std::string& FS) - : PTXTargetMachine(T, TT, CPU, FS, true) { +PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : PTXTargetMachine(T, TT, CPU, FS, RM, true) { } bool PTXTargetMachine::addInstSelector(PassManagerBase &PM, diff --git a/lib/Target/PTX/PTXTargetMachine.h b/lib/Target/PTX/PTXTargetMachine.h index ae42153252..880e8d4add 100644 --- a/lib/Target/PTX/PTXTargetMachine.h +++ b/lib/Target/PTX/PTXTargetMachine.h @@ -32,8 +32,8 @@ class PTXTargetMachine : public LLVMTargetMachine { PTXTargetLowering TLInfo; public: - PTXTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, + PTXTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM, bool is64Bit); virtual const TargetData *getTargetData() const { return &DataLayout; } @@ -61,15 +61,15 @@ class PTXTargetMachine : public LLVMTargetMachine { class PTX32TargetMachine : public PTXTargetMachine { public: - PTX32TargetMachine(const Target &T, const std::string &TT, - const std::string& CPU, const std::string& FS); + PTX32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; // class PTX32TargetMachine class PTX64TargetMachine : public PTXTargetMachine { public: - PTX64TargetMachine(const Target &T, const std::string &TT, - const std::string& CPU, const std::string& FS); + PTX64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; // class PTX32TargetMachine } // namespace llvm diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp index e651330a0e..484bb1af0c 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -93,3 +93,22 @@ extern "C" void LLVMInitializePowerPCMCAsmInfo() { RegisterMCAsmInfoFn C(ThePPC32Target, createPPCMCAsmInfo); RegisterMCAsmInfoFn D(ThePPC64Target, createPPCMCAsmInfo); } + +MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + + if (RM == Reloc::Default) { + Triple T(TT); + if (T.isOSDarwin()) + RM = Reloc::DynamicNoPIC; + else + RM = Reloc::Static; + } + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializePowerPCMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(ThePPC32Target, createPPCMCCodeGenInfo); + TargetRegistry::RegisterMCCodeGenInfo(ThePPC64Target, createPPCMCCodeGenInfo); +} diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index e0ea5adba7..2046673352 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -52,40 +52,32 @@ extern "C" void LLVMInitializePowerPCTarget() { TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer); } - -PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS, bool is64Bit) - : LLVMTargetMachine(T, TT, CPU, FS), +PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool is64Bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS, is64Bit), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), FrameLowering(Subtarget), JITInfo(*this, is64Bit), TLInfo(*this), TSInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { - - if (getRelocationModel() == Reloc::Default) { - if (Subtarget.isDarwin()) - setRelocationModel(Reloc::DynamicNoPIC); - else - setRelocationModel(Reloc::Static); - } } /// Override this for PowerPC. Tail merging happily breaks up instruction issue /// groups, which typically degrades performance. bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; } -PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : PPCTargetMachine(T, TT, CPU, FS, false) { +PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : PPCTargetMachine(T, TT, CPU, FS, RM, false) { } -PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : PPCTargetMachine(T, TT, CPU, FS, true) { +PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : PPCTargetMachine(T, TT, CPU, FS, RM, true) { } @@ -110,19 +102,11 @@ bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, JITCodeEmitter &JCE) { - // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64. // FIXME: This should be moved to TargetJITInfo!! - if (Subtarget.isPPC64()) { - // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many - // instructions to materialize arbitrary global variable + function + - // constant pool addresses. - setRelocationModel(Reloc::PIC_); + if (Subtarget.isPPC64()) // Temporary workaround for the inability of PPC64 JIT to handle jump // tables. DisableJumpTables = true; - } else { - setRelocationModel(Reloc::Static); - } // Inform the subtarget that we are in JIT mode. FIXME: does this break macho // writing? diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h index baf07e3498..bdec0861cf 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.h +++ b/lib/Target/PowerPC/PPCTargetMachine.h @@ -40,9 +40,9 @@ class PPCTargetMachine : public LLVMTargetMachine { InstrItineraryData InstrItins; public: - PPCTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, - bool is64Bit); + PPCTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool is64Bit); virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const PPCFrameLowering *getFrameLowering() const { @@ -77,16 +77,16 @@ public: /// class PPC32TargetMachine : public PPCTargetMachine { public: - PPC32TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + PPC32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; /// PPC64TargetMachine - PowerPC 64-bit target machine. /// class PPC64TargetMachine : public PPCTargetMachine { public: - PPC64TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + PPC64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; } // end namespace llvm diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp index bdece2a486..76a5873350 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -65,3 +65,17 @@ extern "C" void LLVMInitializeSparcMCAsmInfo() { RegisterMCAsmInfo<SparcELFMCAsmInfo> X(TheSparcTarget); RegisterMCAsmInfo<SparcELFMCAsmInfo> Y(TheSparcV9Target); } + +MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeSparcMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheSparcTarget, + createSparcMCCodeGenInfo); + TargetRegistry::RegisterMCCodeGenInfo(TheSparcV9Target, + createSparcMCCodeGenInfo); +} + diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index cbe6d8754e..218c4bc9bc 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -24,10 +24,10 @@ extern "C" void LLVMInitializeSparcTarget() { /// SparcTargetMachine ctor - Create an ILP32 architecture model /// -SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS, bool is64bit) - : LLVMTargetMachine(T, TT, CPU, FS), +SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool is64bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS, is64bit), DataLayout(Subtarget.getDataLayout()), TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), @@ -51,15 +51,15 @@ bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, } SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : SparcTargetMachine(T, TT, CPU, FS, false) { + StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : SparcTargetMachine(T, TT, CPU, FS, RM, false) { } SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : SparcTargetMachine(T, TT, CPU, FS, true) { + StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : SparcTargetMachine(T, TT, CPU, FS, RM, true) { } diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h index 799fc497f4..49d36bb066 100644 --- a/lib/Target/Sparc/SparcTargetMachine.h +++ b/lib/Target/Sparc/SparcTargetMachine.h @@ -33,9 +33,9 @@ class SparcTargetMachine : public LLVMTargetMachine { SparcInstrInfo InstrInfo; SparcFrameLowering FrameLowering; public: - SparcTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, - bool is64bit); + SparcTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool is64bit); virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { @@ -62,16 +62,16 @@ public: /// class SparcV8TargetMachine : public SparcTargetMachine { public: - SparcV8TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + SparcV8TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; /// SparcV9TargetMachine - Sparc 64-bit target machine /// class SparcV9TargetMachine : public SparcTargetMachine { public: - SparcV9TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + SparcV9TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; } // end namespace llvm diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp index 70d6c49302..79c41d889b 100644 --- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -67,3 +67,16 @@ extern "C" void LLVMInitializeSystemZMCSubtargetInfo() { extern "C" void LLVMInitializeSystemZMCAsmInfo() { RegisterMCAsmInfo<SystemZMCAsmInfo> X(TheSystemZTarget); } + +MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + if (RM == Reloc::Default) + RM = Reloc::Static; + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeSystemZMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheSystemZTarget, + createSystemZMCCodeGenInfo); +} diff --git a/lib/Target/SystemZ/SystemZTargetMachine.cpp b/lib/Target/SystemZ/SystemZTargetMachine.cpp index 48298cc744..afa455ea25 100644 --- a/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -21,18 +21,15 @@ extern "C" void LLVMInitializeSystemZTarget() { /// SystemZTargetMachine ctor - Create an ILP64 architecture model /// SystemZTargetMachine::SystemZTargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), + StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS), DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32" "-f64:64:64-f128:128:128-a0:16:16-n32:64"), InstrInfo(*this), TLInfo(*this), TSInfo(*this), FrameLowering(Subtarget) { - - if (getRelocationModel() == Reloc::Default) - setRelocationModel(Reloc::Static); } bool SystemZTargetMachine::addInstSelector(PassManagerBase &PM, diff --git a/lib/Target/SystemZ/SystemZTargetMachine.h b/lib/Target/SystemZ/SystemZTargetMachine.h index e40b556c0c..9008b80e21 100644 --- a/lib/Target/SystemZ/SystemZTargetMachine.h +++ b/lib/Target/SystemZ/SystemZTargetMachine.h @@ -37,8 +37,8 @@ class SystemZTargetMachine : public LLVMTargetMachine { SystemZSelectionDAGInfo TSInfo; SystemZFrameLowering FrameLowering; public: - SystemZTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + SystemZTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const TargetFrameLowering *getFrameLowering() const { return &FrameLowering; diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp index 74a1f4e8da..865e41aa1d 100644 --- a/lib/Target/TargetMachine.cpp +++ b/lib/Target/TargetMachine.cpp @@ -40,7 +40,6 @@ namespace llvm { bool JITExceptionHandling; bool JITEmitDebugInfo; bool JITEmitDebugInfoToDisk; - Reloc::Model RelocationModel; CodeModel::Model CMModel; bool GuaranteedTailCallOpt; unsigned StackAlignmentOverride; @@ -143,21 +142,6 @@ EmitJitDebugInfoToDisk("jit-emit-debug-to-disk", cl::location(JITEmitDebugInfoToDisk), cl::init(false)); -static cl::opt<llvm::Reloc::Model, true> -DefRelocationModel("relocation-model", - cl::desc("Choose relocation model"), - cl::location(RelocationModel), - cl::init(Reloc::Default), - cl::values( - clEnumValN(Reloc::Default, "default", - "Target default relocation model"), - clEnumValN(Reloc::Static, "static", - "Non-relocatable code"), - clEnumValN(Reloc::PIC_, "pic", - "Fully relocatable, position independent code"), - clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic", - "Relocatable external references, non-relocatable code"), - clEnumValEnd)); static cl::opt<llvm::CodeModel::Model, true> DefCodeModel("code-model", cl::desc("Choose code model"), @@ -236,13 +220,10 @@ TargetMachine::~TargetMachine() { /// getRelocationModel - Returns the code generation relocation model. The /// choices are static, PIC, and dynamic-no-pic, and target default. -Reloc::Model TargetMachine::getRelocationModel() { - return RelocationModel; -} - -/// setRelocationModel - Sets the code generation relocation model. -void TargetMachine::setRelocationModel(Reloc::Model Model) { - RelocationModel = Model; +Reloc::Model TargetMachine::getRelocationModel() const { + if (!CodeGenInfo) + return Reloc::Default; + return CodeGenInfo->getRelocationModel(); } /// getCodeModel - Returns the code model. The choices are small, kernel, diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp index a60b69f2fb..9e415a87f5 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -338,3 +338,50 @@ extern "C" void LLVMInitializeX86MCAsmInfo() { RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo); RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo); } + +MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + + Triple T(TT); + bool is64Bit = T.getArch() == Triple::x86_64; + + if (RM == Reloc::Default) { + // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. + // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we + // use static relocation model by default. + if (T.isOSDarwin()) { + if (is64Bit) + RM = Reloc::PIC_; + else + RM = Reloc::DynamicNoPIC; + } else if (T.isOSWindows() && is64Bit) + RM = Reloc::PIC_; + else + RM = Reloc::Static; + } + + // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC + // is defined as a model for code which may be used in static or dynamic + // executables but not necessarily a shared library. On X86-32 we just + // compile in -static mode, in x86-64 we use PIC. + if (RM == Reloc::DynamicNoPIC) { + if (is64Bit) + RM = Reloc::PIC_; + else if (!T.isOSDarwin()) + RM = Reloc::Static; + } + + // If we are on Darwin, disallow static relocation model in X86-64 mode, since + // the Mach-O file format doesn't support it. + if (RM == Reloc::Static && T.isOSDarwin() && is64Bit) + RM = Reloc::PIC_; + + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeX86MCCodeGenInfo() { + // Register the target asm info. + RegisterMCCodeGenInfoFn A(TheX86_32Target, createX86MCCodeGenInfo); + RegisterMCCodeGenInfoFn B(TheX86_64Target, createX86MCCodeGenInfo); +} diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index 9cab0e0890..770dbbba1d 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -65,10 +65,10 @@ extern "C" void LLVMInitializeX86Target() { } -X86_32TargetMachine::X86_32TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : X86TargetMachine(T, TT, CPU, FS, false), +X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : X86TargetMachine(T, TT, CPU, FS, RM, false), DataLayout(getSubtargetImpl()->isTargetDarwin() ? "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-n8:16:32" : (getSubtargetImpl()->isTargetCygMing() || @@ -82,10 +82,10 @@ X86_32TargetMachine::X86_32TargetMachine(const Target &T, const std::string &TT, } -X86_64TargetMachine::X86_64TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : X86TargetMachine(T, TT, CPU, FS, true), +X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : X86TargetMachine(T, TT, CPU, FS, RM, true), DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-n8:16:32:64"), InstrInfo(*this), TSInfo(*this), @@ -95,52 +95,13 @@ X86_64TargetMachine::X86_64TargetMachine(const Target &T, const std::string &TT, /// X86TargetMachine ctor - Create an X86 target. /// -X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS, bool is64Bit) - : LLVMTargetMachine(T, TT, CPU, FS), +X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool is64Bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit), FrameLowering(*this, Subtarget), ELFWriterInfo(is64Bit, true) { - DefRelocModel = getRelocationModel(); - - // If no relocation model was picked, default as appropriate for the target. - if (getRelocationModel() == Reloc::Default) { - // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. - // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we - // use static relocation model by default. - if (Subtarget.isTargetDarwin()) { - if (Subtarget.is64Bit()) - setRelocationModel(Reloc::PIC_); - else - setRelocationModel(Reloc::DynamicNoPIC); - } else if (Subtarget.isTargetWin64()) - setRelocationModel(Reloc::PIC_); - else - setRelocationModel(Reloc::Static); - } - - assert(getRelocationModel() != Reloc::Default && - "Relocation mode not picked"); - - // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC - // is defined as a model for code which may be used in static or dynamic - // executables but not necessarily a shared library. On X86-32 we just - // compile in -static mode, in x86-64 we use PIC. - if (getRelocationModel() == Reloc::DynamicNoPIC) { - if (is64Bit) - setRelocationModel(Reloc::PIC_); - else if (!Subtarget.isTargetDarwin()) - setRelocationModel(Reloc::Static); - } - - // If we are on Darwin, disallow static relocation model in X86-64 mode, since - // the Mach-O file format doesn't support it. - if (getRelocationModel() == Reloc::Static && - Subtarget.isTargetDarwin() && - is64Bit) - setRelocationModel(Reloc::PIC_); - // Determine the PICStyle based on the target selected. if (getRelocationModel() == Reloc::Static) { // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None. @@ -161,10 +122,6 @@ X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT, Subtarget.setPICStyle(PICStyles::GOT); } - // Finally, if we have "none" as our PIC style, force to static mode. - if (Subtarget.getPICStyle() == PICStyles::None) - setRelocationModel(Reloc::Static); - // default to hard float ABI if (FloatABIType == FloatABI::Default) FloatABIType = FloatABI::Hard; @@ -210,15 +167,6 @@ bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM, bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, JITCodeEmitter &JCE) { - // FIXME: Move this to TargetJITInfo! - // On Darwin, do not override 64-bit setting made in X86TargetMachine(). - if (DefRelocModel == Reloc::Default && - (!Subtarget.isTargetDarwin() || !Subtarget.is64Bit())) { - setRelocationModel(Reloc::Static); - Subtarget.setPICStyle(PICStyles::None); - } - - PM.add(createX86JITCodeEmitterPass(*this, JCE)); return false; diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index 885334a365..c19efccd04 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -29,12 +29,12 @@ namespace llvm { class formatted_raw_ostream; +class StringRef; class X86TargetMachine : public LLVMTargetMachine { X86Subtarget Subtarget; X86FrameLowering FrameLowering; X86ELFWriterInfo ELFWriterInfo; - Reloc::Model DefRelocModel; // Reloc model before it's overridden. private: // We have specific defaults for X86. @@ -42,9 +42,9 @@ private: virtual void setCodeModelForStatic(); public: - X86TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, - bool is64Bit); + X86TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool is64Bit); virtual const X86InstrInfo *getInstrInfo() const { llvm_unreachable("getInstrInfo not implemented"); @@ -87,8 +87,8 @@ class X86_32TargetMachine : public X86TargetMachine { X86TargetLowering TLInfo; X86JITInfo JITInfo; public: - X86_32TargetMachine(const Target &T, const std::string &M, - const std::string &CPU, const std::string &FS); + X86_32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const X86TargetLowering *getTargetLowering() const { return &TLInfo; @@ -113,8 +113,8 @@ class X86_64TargetMachine : public X86TargetMachine { X86TargetLowering TLInfo; X86JITInfo JITInfo; public: - X86_64TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + X86_64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const X86TargetLowering *getTargetLowering() const { return &TLInfo; diff --git a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp index 104170c328..f44e62cf79 100644 --- a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -75,3 +75,14 @@ static MCAsmInfo *createXCoreMCAsmInfo(const Target &T, StringRef TT) { extern "C" void LLVMInitializeXCoreMCAsmInfo() { RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo); } + +MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeXCoreMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheXCoreTarget, + createXCoreMCCodeGenInfo); +} diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp index 342966ae5c..0c0267dd69 100644 --- a/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/lib/Target/XCore/XCoreTargetMachine.cpp @@ -19,10 +19,10 @@ using namespace llvm; /// XCoreTargetMachine ctor - Create an ILP32 architecture model /// -XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), +XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS), DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-" "i16:16:32-i32:32:32-i64:32:32-n32"), diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h index 6235ac3a6a..f782e173d4 100644 --- a/lib/Target/XCore/XCoreTargetMachine.h +++ b/lib/Target/XCore/XCoreTargetMachine.h @@ -32,8 +32,8 @@ class XCoreTargetMachine : public LLVMTargetMachine { XCoreTargetLowering TLInfo; XCoreSelectionDAGInfo TSInfo; public: - XCoreTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + XCoreTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const XCoreFrameLowering *getFrameLowering() const { diff --git a/test/CodeGen/Thumb2/thumb2-bcc.ll b/test/CodeGen/Thumb2/thumb2-bcc.ll index 70febc060e..0f7605402c 100644 --- a/test/CodeGen/Thumb2/thumb2-bcc.ll +++ b/test/CodeGen/Thumb2/thumb2-bcc.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s -; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep it ; If-conversion defeats the purpose of this test, which is to check CBZ ; generation, so use memory barrier instruction to make sure it doesn't ; happen and we get actual branches. diff --git a/tools/llc/llc.cpp b/tools/llc/llc.cpp index c40298c3b1..f1d4dbcad5 100644 --- a/tools/llc/llc.cpp +++ b/tools/llc/llc.cpp @@ -76,6 +76,21 @@ MAttrs("mattr", cl::desc("Target specific attributes (-mattr=help for details)"), cl::value_desc("a1,+a2,-a3,...")); +static cl::opt<Reloc::Model> +RelocModel("relocation-model", + cl::desc("Choose relocation model"), + cl::init(Reloc::Default), + cl::values( + clEnumValN(Reloc::Default, "default", + "Target default relocation model"), + clEnumValN(Reloc::Static, "static", + "Non-relocatable code"), + clEnumValN(Reloc::PIC_, "pic", + "Fully relocatable, position independent code"), + clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic", + "Relocatable external references, non-relocatable code"), + clEnumValEnd)); + static cl::opt<bool> RelaxAll("mc-relax-all", cl::desc("When used with filetype=obj, " @@ -202,6 +217,7 @@ int main(int argc, char **argv) { // Initialize targets first, so that --version shows registered targets. InitializeAllTargets(); InitializeAllMCAsmInfos(); + InitializeAllMCCodeGenInfos(); InitializeAllMCSubtargetInfos(); InitializeAllAsmPrinters(); InitializeAllAsmParsers(); @@ -272,7 +288,7 @@ int main(int argc, char **argv) { std::auto_ptr<TargetMachine> target(TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU, - FeaturesStr)); + FeaturesStr, RelocModel)); assert(target.get() && "Could not allocate target machine!"); TargetMachine &Target = *target.get(); diff --git a/tools/lli/lli.cpp b/tools/lli/lli.cpp index 014925c1a9..da03ddd4b0 100644 --- a/tools/lli/lli.cpp +++ b/tools/lli/lli.cpp @@ -108,6 +108,21 @@ namespace { NoLazyCompilation("disable-lazy-compilation", cl::desc("Disable JIT lazy compilation"), cl::init(false)); + + cl::opt<Reloc::Model> + RelocModel("relocation-model", + cl::desc("Choose relocation model"), + cl::init(Reloc::Default), + cl::values( + clEnumValN(Reloc::Default, "default", + "Target default relocation model"), + clEnumValN(Reloc::Static, "static", + "Non-relocatable code"), + clEnumValN(Reloc::PIC_, "pic", + "Fully relocatable, position independent code"), + clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic", + "Relocatable external references, non-relocatable code"), + clEnumValEnd)); } static ExecutionEngine *EE = 0; @@ -164,6 +179,7 @@ int main(int argc, char **argv, char * const *envp) { builder.setMArch(MArch); builder.setMCPU(MCPU); builder.setMAttrs(MAttrs); + builder.setRelocationModel(RelocModel); builder.setErrorStr(&ErrorMsg); builder.setEngineKind(ForceInterpreter ? EngineKind::Interpreter diff --git a/tools/llvm-mc/llvm-mc.cpp b/tools/llvm-mc/llvm-mc.cpp index 1633ae3147..e2de05542b 100644 --- a/tools/llvm-mc/llvm-mc.cpp +++ b/tools/llvm-mc/llvm-mc.cpp @@ -111,6 +111,21 @@ MCPU("mcpu", cl::value_desc("cpu-name"), cl::init("")); +static cl::opt<Reloc::Model> +RelocModel("relocation-model", + cl::desc("Choose relocation model"), + cl::init(Reloc::Default), + cl::values( + clEnumValN(Reloc::Default, "default", + "Target default relocation model"), + clEnumValN(Reloc::Static, "static", + "Non-relocatable code"), + clEnumValN(Reloc::PIC_, "pic", + "Fully relocatable, position independent code"), + clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic", + "Relocatable external references, non-relocatable code"), + clEnumValEnd)); + static cl::opt<bool> NoInitialTextSection("n", cl::desc("Don't assume assembly file starts " "in the text section")); @@ -321,7 +336,8 @@ static int AssembleInput(const char *ProgName) { // the .cpu and .code16 directives). OwningPtr<TargetMachine> TM(TheTarget->createTargetMachine(TripleName, MCPU, - FeaturesStr)); + FeaturesStr, + RelocModel)); if (!TM) { errs() << ProgName << ": error: could not create target for triple '" @@ -440,6 +456,7 @@ int main(int argc, char **argv) { // FIXME: We shouldn't need to initialize the Target(Machine)s. llvm::InitializeAllTargets(); llvm::InitializeAllMCAsmInfos(); + llvm::InitializeAllMCCodeGenInfos(); llvm::InitializeAllMCInstrInfos(); llvm::InitializeAllMCRegisterInfos(); llvm::InitializeAllMCSubtargetInfos(); diff --git a/tools/llvm-objdump/llvm-objdump.cpp b/tools/llvm-objdump/llvm-objdump.cpp index 4079e4aabe..59586ce761 100644 --- a/tools/llvm-objdump/llvm-objdump.cpp +++ b/tools/llvm-objdump/llvm-objdump.cpp @@ -270,6 +270,7 @@ int main(int argc, char **argv) { // FIXME: We shouldn't need to initialize the Target(Machine)s. llvm::InitializeAllTargets(); llvm::InitializeAllMCAsmInfos(); + llvm::InitializeAllMCCodeGenInfos(); llvm::InitializeAllAsmPrinters(); llvm::InitializeAllAsmParsers(); llvm::InitializeAllDisassemblers(); diff --git a/tools/lto/LTOCodeGenerator.cpp b/tools/lto/LTOCodeGenerator.cpp index 3fce45677c..28cfa9cc75 100644 --- a/tools/lto/LTOCodeGenerator.cpp +++ b/tools/lto/LTOCodeGenerator.cpp @@ -75,6 +75,7 @@ LTOCodeGenerator::LTOCodeGenerator() { InitializeAllTargets(); InitializeAllMCAsmInfos(); + InitializeAllMCCodeGenInfos(); InitializeAllMCRegisterInfos(); InitializeAllMCSubtargetInfos(); InitializeAllAsmPrinters(); @@ -252,15 +253,16 @@ bool LTOCodeGenerator::determineTarget(std::string& errMsg) // The relocation model is actually a static member of TargetMachine // and needs to be set before the TargetMachine is instantiated. + Reloc::Model RelocModel = Reloc::Default; switch( _codeModel ) { case LTO_CODEGEN_PIC_MODEL_STATIC: - TargetMachine::setRelocationModel(Reloc::Static); + RelocModel = Reloc::Static; break; case LTO_CODEGEN_PIC_MODEL_DYNAMIC: - TargetMachine::setRelocationModel(Reloc::PIC_); + RelocModel = Reloc::PIC_; break; case LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC: - TargetMachine::setRelocationModel(Reloc::DynamicNoPIC); + RelocModel = Reloc::DynamicNoPIC; break; } @@ -268,7 +270,8 @@ bool LTOCodeGenerator::determineTarget(std::string& errMsg) SubtargetFeatures Features; Features.getDefaultSubtargetFeatures(llvm::Triple(Triple)); std::string FeatureStr = Features.getString(); - _target = march->createTargetMachine(Triple, _mCpu, FeatureStr); + _target = march->createTargetMachine(Triple, _mCpu, FeatureStr, + RelocModel); } return false; } diff --git a/tools/lto/LTOModule.cpp b/tools/lto/LTOModule.cpp index 92b2e9aa1a..0ca96bc28a 100644 --- a/tools/lto/LTOModule.cpp +++ b/tools/lto/LTOModule.cpp @@ -136,6 +136,7 @@ LTOModule *LTOModule::makeLTOModule(MemoryBuffer *buffer, static bool Initialized = false; if (!Initialized) { InitializeAllTargets(); + InitializeAllMCCodeGenInfos(); InitializeAllMCAsmInfos(); InitializeAllMCSubtargetInfos(); InitializeAllAsmParsers(); |