diff options
| -rw-r--r-- | lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 19 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCCodeEmitter.cpp | 23 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 4 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 4 |
4 files changed, 17 insertions, 33 deletions
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index 34bd483ee0..31c73aeff5 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -48,10 +48,8 @@ public: SmallVectorImpl<MCFixup> &Fixups) const; unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups) const; - unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl<MCFixup> &Fixups) const; - unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl<MCFixup> &Fixups) const; + unsigned getS16ImmEncoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups) const; unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups) const; unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, @@ -136,18 +134,7 @@ unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, return 0; } -unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl<MCFixup> &Fixups) const { - const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); - - // Add a fixup for the branch target. - Fixups.push_back(MCFixup::Create(2, MO.getExpr(), - (MCFixupKind)PPC::fixup_ppc_half16)); - return 0; -} - -unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo, +unsigned PPCMCCodeEmitter::getS16ImmEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups) const { const MCOperand &MO = MI.getOperand(OpNo); if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index 14f9ff64d2..40e4968bb4 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -64,8 +64,7 @@ namespace { unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const; - unsigned getHA16Encoding(const MachineInstr &MI, unsigned OpNo) const; - unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const; + unsigned getS16ImmEncoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const; @@ -194,21 +193,19 @@ unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI, return 0; } -unsigned PPCCodeEmitter::getHA16Encoding(const MachineInstr &MI, - unsigned OpNo) const { +unsigned PPCCodeEmitter::getS16ImmEncoding(const MachineInstr &MI, + unsigned OpNo) const { const MachineOperand &MO = MI.getOperand(OpNo); if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); - MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_high)); - return 0; -} + unsigned RelocID; + switch (MO.getTargetFlags() & PPCII::MO_ACCESS_MASK) { + default: llvm_unreachable("Unsupported target operand flags!"); + case PPCII::MO_HA16: RelocID = PPC::reloc_absolute_high; break; + case PPCII::MO_LO16: RelocID = PPC::reloc_absolute_low; break; + } -unsigned PPCCodeEmitter::getLO16Encoding(const MachineInstr &MI, - unsigned OpNo) const { - const MachineOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); - - MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low)); + MCE.addRelocation(GetRelocation(MO, RelocID)); return 0; } diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 4b3c22d7cf..c1071b1976 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -25,12 +25,12 @@ def u16imm64 : Operand<i64> { } def symbolHi64 : Operand<i64> { let PrintMethod = "printSymbolHi"; - let EncoderMethod = "getHA16Encoding"; + let EncoderMethod = "getS16ImmEncoding"; let ParserMatchClass = PPCS16ImmAsmOperand; } def symbolLo64 : Operand<i64> { let PrintMethod = "printSymbolLo"; - let EncoderMethod = "getLO16Encoding"; + let EncoderMethod = "getS16ImmEncoding"; let ParserMatchClass = PPCS16ImmAsmOperand; } def tocentry : Operand<iPTR> { diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index e87fa8f342..16a102f6a2 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -458,12 +458,12 @@ def aaddr : Operand<iPTR> { } def symbolHi: Operand<i32> { let PrintMethod = "printSymbolHi"; - let EncoderMethod = "getHA16Encoding"; + let EncoderMethod = "getS16ImmEncoding"; let ParserMatchClass = PPCS16ImmAsmOperand; } def symbolLo: Operand<i32> { let PrintMethod = "printSymbolLo"; - let EncoderMethod = "getLO16Encoding"; + let EncoderMethod = "getS16ImmEncoding"; let ParserMatchClass = PPCS16ImmAsmOperand; } def PPCCRBitMaskOperand : AsmOperandClass { |