diff options
| -rw-r--r-- | lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 32 | ||||
| -rw-r--r-- | test/MC/X86/x86-16.s | 52 |
2 files changed, 70 insertions, 14 deletions
diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index d3879e6c4c..ae4fc2b3b7 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -57,6 +57,24 @@ public: return (STI.getFeatureBits() & X86::Mode16Bit) != 0; } + /// Is16BitMemOperand - Return true if the specified instruction has + /// a 16-bit memory operand. Op specifies the operand # of the memoperand. + bool Is16BitMemOperand(const MCInst &MI, unsigned Op) const { + const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); + const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); + const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); + + if (is16BitMode() && BaseReg.getReg() == 0 && + Disp.isImm() && Disp.getImm() < 0x10000) + return true; + if ((BaseReg.getReg() != 0 && + X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || + (IndexReg.getReg() != 0 && + X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) + return true; + return false; + } + unsigned GetX86RegNum(const MCOperand &MO) const { return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; } @@ -250,20 +268,6 @@ static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) { } #endif -/// Is16BitMemOperand - Return true if the specified instruction has -/// a 16-bit memory operand. Op specifies the operand # of the memoperand. -static bool Is16BitMemOperand(const MCInst &MI, unsigned Op) { - const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); - const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); - - if ((BaseReg.getReg() != 0 && - X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || - (IndexReg.getReg() != 0 && - X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) - return true; - return false; -} - /// StartsWithGlobalOffsetTable - Check if this expression starts with /// _GLOBAL_OFFSET_TABLE_ and if it is of the form /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF diff --git a/test/MC/X86/x86-16.s b/test/MC/X86/x86-16.s index e395a779f2..4f2108cbde 100644 --- a/test/MC/X86/x86-16.s +++ b/test/MC/X86/x86-16.s @@ -319,6 +319,10 @@ cmovnae %bx,%bx // CHECK: encoding: [0x9b] fwait +// CHECK: [0x65,0x66,0x8b,0x06,0x7c,0x00] +// FIXME: This is a correct bug poor encoding: Use 65 66 a1 7c 00 + movl %gs:124, %eax + // CHECK: pusha // CHECK: encoding: [0x60] pusha @@ -701,6 +705,54 @@ pshufw $90, %mm4, %mm0 // CHECK: encoding: [0xdf,0xe9] fucompi +// CHECK: fldcw 32493 +// CHECK: encoding: [0xd9,0x2e,0xed,0x7e] + fldcww 0x7eed + +// CHECK: fldcw 32493 +// CHECK: encoding: [0xd9,0x2e,0xed,0x7e] + fldcw 0x7eed + +// CHECK: fnstcw 32493 +// CHECK: encoding: [0xd9,0x3e,0xed,0x7e] + fnstcww 0x7eed + +// CHECK: fnstcw 32493 +// CHECK: encoding: [0xd9,0x3e,0xed,0x7e] + fnstcw 0x7eed + +// CHECK: wait +// CHECK: encoding: [0x9b] + fstcww 0x7eed + +// CHECK: wait +// CHECK: encoding: [0x9b] + fstcw 0x7eed + +// CHECK: fnstsw 32493 +// CHECK: encoding: [0xdd,0x3e,0xed,0x7e] + fnstsww 0x7eed + +// CHECK: fnstsw 32493 +// CHECK: encoding: [0xdd,0x3e,0xed,0x7e] + fnstsw 0x7eed + +// CHECK: wait +// CHECK: encoding: [0x9b] + fstsww 0x7eed + +// CHECK: wait +// CHECK: encoding: [0x9b] + fstsw 0x7eed + +// CHECK: verr 32493 +// CHECK: encoding: [0x0f,0x00,0x26,0xed,0x7e] + verrw 0x7eed + +// CHECK: verr 32493 +// CHECK: encoding: [0x0f,0x00,0x26,0xed,0x7e] + verr 0x7eed + // CHECK: wait // CHECK: encoding: [0x9b] fclex |