diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 9 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 1 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 8 |
3 files changed, 13 insertions, 5 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index b4958d6d94..5acb6fa1fa 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -407,6 +407,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, if (InstanceNo > 0) VRBaseMap.erase(SDOperand(Node, ResNo)); bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo),SrcReg)); + isNew; // Silence compiler warning. assert(isNew && "Node emitted out of order - early"); return; } @@ -465,6 +466,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, if (InstanceNo > 0) VRBaseMap.erase(SDOperand(Node, ResNo)); bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo), VRBase)); + isNew; // Silence compiler warning. assert(isNew && "Node emitted out of order - early"); } @@ -522,6 +524,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, } bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase)); + isNew; // Silence compiler warning. assert(isNew && "Node emitted out of order - early"); } } @@ -719,9 +722,11 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, if (VRBase) { // Grab the destination register +#ifndef NDEBUG const TargetRegisterClass *DRC = MRI.getRegClass(VRBase); assert(SRC && DRC && SRC == DRC && "Source subregister and destination must have the same class"); +#endif } else { // Create the reg assert(SRC && "Couldn't find source register class"); @@ -772,6 +777,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg"); bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,0), VRBase)); + isNew; // Silence compiler warning. assert(isNew && "Node emitted out of order - early"); } @@ -799,10 +805,10 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, unsigned NumResults = CountResults(Node); unsigned NodeOperands = CountOperands(Node); unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node); - unsigned NumMIOperands = NodeOperands + NumResults; bool HasPhysRegOuts = (NumResults > II.getNumDefs()) && II.getImplicitDefs() != 0; #ifndef NDEBUG + unsigned NumMIOperands = NodeOperands + NumResults; assert((II.getNumOperands() == NumMIOperands || HasPhysRegOuts || II.isVariadic()) && "#operands for dag node doesn't match .td file!"); @@ -999,6 +1005,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, assert(I->Reg && "Unknown physical register!"); unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC); bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)); + isNew; // Silence compiler warning. assert(isNew && "Node emitted out of order - early"); TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg, SU->CopyDstRC, SU->CopySrcRC); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 9c61ed8ab0..f0d9f36d08 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1317,6 +1317,7 @@ namespace { void remove(SUnit *SU) { assert(!Queue.empty() && "Queue is empty!"); size_t RemovedNum = Queue.erase(SU); + RemovedNum; // Silence compiler warning. assert(RemovedNum > 0 && "Not in queue!"); assert(RemovedNum == 1 && "Multiple times in the queue!"); SU->NodeQueueId = 0; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index f79ad0290a..3cc815283b 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -807,7 +807,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG, unsigned NumRegs = TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, RegisterVT); - + NumRegs; // Silence a compiler warning. assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); assert(RegisterVT == Parts[0].getValueType() && @@ -1024,6 +1024,7 @@ static void getCopyToParts(SelectionDAG &DAG, DAG.getTargetLoweringInfo() .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, RegisterVT); + NumRegs; // Silence a compiler warning. unsigned NumElements = MVT::getVectorNumElements(ValueVT); assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); @@ -3752,14 +3753,13 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, // If this is an expanded reference, add the rest of the regs to Regs. if (NumRegs != 1) { TargetRegisterClass::iterator I = PhysReg.second->begin(); - TargetRegisterClass::iterator E = PhysReg.second->end(); for (; *I != PhysReg.first; ++I) - assert(I != E && "Didn't find reg!"); + assert(I != PhysReg.second->end() && "Didn't find reg!"); // Already added the first reg. --NumRegs; ++I; for (; NumRegs; --NumRegs, ++I) { - assert(I != E && "Ran out of registers to allocate!"); + assert(I != PhysReg.second->end() && "Ran out of registers to allocate!"); Regs.push_back(*I); } } |