diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 4 | ||||
| -rw-r--r-- | test/CodeGen/X86/bswap-vector.ll | 17 |
2 files changed, 19 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 1c5c9a2492..2483184dee 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -268,9 +268,9 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { EVT NVT = Op.getValueType(); SDLoc dl(N); - unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); + unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(); return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), - DAG.getConstant(DiffBits, TLI.getPointerTy())); + DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT))); } SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { diff --git a/test/CodeGen/X86/bswap-vector.ll b/test/CodeGen/X86/bswap-vector.ll index a18fd68865..3c931db2e2 100644 --- a/test/CodeGen/X86/bswap-vector.ll +++ b/test/CodeGen/X86/bswap-vector.ll @@ -122,6 +122,23 @@ entry: ; CHECK-AVX2-NEXT: retq } +declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>) + +define <4 x i16> @test7(<4 x i16> %v) #0 { +entry: + %r = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %v) + ret <4 x i16> %r + +; CHECK-SSSE3-LABEL: @test7 +; CHECK-SSSE3: pshufb +; CHECK-SSSE3: psrld $16 +; CHECK-SSSE3-NEXT: retq + +; CHECK-AVX2-LABEL: @test7 +; CHECK-AVX2: vpshufb +; CHECK-AVX2: vpsrld $16 +; CHECK-AVX2-NEXT: retq +} attributes #0 = { nounwind uwtable } |