diff options
| -rw-r--r-- | include/llvm/IR/IntrinsicsMips.td | 6 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsMSAInstrFormats.td | 6 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsMSAInstrInfo.td | 18 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsSEISelLowering.cpp | 6 | ||||
| -rw-r--r-- | test/CodeGen/Mips/msa/special.ll | 26 |
5 files changed, 62 insertions, 0 deletions
diff --git a/include/llvm/IR/IntrinsicsMips.td b/include/llvm/IR/IntrinsicsMips.td index 4824ae5570..0634c18d09 100644 --- a/include/llvm/IR/IntrinsicsMips.td +++ b/include/llvm/IR/IntrinsicsMips.td @@ -1251,6 +1251,12 @@ def int_mips_ldi_w : GCCBuiltin<"__builtin_msa_ldi_w">, def int_mips_ldi_d : GCCBuiltin<"__builtin_msa_ldi_d">, Intrinsic<[llvm_v2i64_ty], [llvm_i32_ty], [IntrNoMem]>; +// This instruction is part of the MSA spec but it does not share the +// __builtin_msa prefix because it operates on the GPR registers. +def int_mips_lsa : GCCBuiltin<"__builtin_mips_lsa">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], + [IntrNoMem]>; + def int_mips_madd_q_h : GCCBuiltin<"__builtin_msa_madd_q_h">, Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td index 1a8dafb9e3..9a3a8cdb61 100644 --- a/lib/Target/Mips/MipsMSAInstrFormats.td +++ b/lib/Target/Mips/MipsMSAInstrFormats.td @@ -314,3 +314,9 @@ class MSA_VECS10_FMT<bits<5> major, bits<6> minor>: MSAInst { let Inst{25-21} = major; let Inst{5-0} = minor; } + +class SPECIAL_LSA_FMT: MSAInst { + let Inst{25-21} = 0b000000; + let Inst{10-8} = 0b000; + let Inst{5-0} = 0b000101; +} diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 778fda1e64..992340d1f9 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -61,6 +61,10 @@ def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", // Operands +def uimm2 : Operand<i32> { + let PrintMethod = "printUnsignedImm"; +} + def uimm3 : Operand<i32> { let PrintMethod = "printUnsignedImm"; } @@ -109,6 +113,8 @@ def vsplat_simm5 : Operand<vAny>; def vsplat_simm10 : Operand<vAny>; +def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>; + // Pattern fragments def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), (MipsVExtractSExt node:$vec, node:$idx, i8)>; @@ -762,6 +768,8 @@ class LDI_H_ENC : MSA_I10_FMT<0b010, 0b01, 0b001100>; class LDI_W_ENC : MSA_I10_FMT<0b010, 0b10, 0b001100>; class LDI_D_ENC : MSA_I10_FMT<0b010, 0b11, 0b001100>; +class LSA_ENC : SPECIAL_LSA_FMT; + class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; @@ -2038,6 +2046,14 @@ class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128H>; class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128W>; class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128D>; +class LSA_DESC { + dag OutOperandList = (outs GPR32:$rd); + dag InOperandList = (ins GPR32:$rs, GPR32:$rt, uimm2:$sa); + string AsmString = "lsa\t$rd, $rs, $rt, $sa"; + list<dag> Pattern = [(set GPR32:$rd, (add GPR32:$rs, (shl GPR32:$rt, + immZExt2Lsa:$sa)))]; + InstrItinClass Itinerary = NoItinerary; +} class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, MSA128HOpnd>; @@ -2893,6 +2909,8 @@ def LDI_H : LDI_H_ENC, LDI_H_DESC; def LDI_W : LDI_W_ENC, LDI_W_DESC; def LDI_D : LDI_D_ENC, LDI_D_DESC; +def LSA : LSA_ENC, LSA_DESC; + def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index 9b23304cbd..def8957632 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -1403,6 +1403,12 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_ldi_w: case Intrinsic::mips_ldi_d: return lowerMSASplatImm(Op, 1, DAG); + case Intrinsic::mips_lsa: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), + DAG.getNode(ISD::SHL, SDLoc(Op), ResTy, + Op->getOperand(2), Op->getOperand(3))); + } case Intrinsic::mips_maddv_b: case Intrinsic::mips_maddv_h: case Intrinsic::mips_maddv_w: diff --git a/test/CodeGen/Mips/msa/special.ll b/test/CodeGen/Mips/msa/special.ll new file mode 100644 index 0000000000..60a4369dfb --- /dev/null +++ b/test/CodeGen/Mips/msa/special.ll @@ -0,0 +1,26 @@ +; Test the MSA intrinsics that are encoded with the SPECIAL instruction format. + +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s + +define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind { +entry: + %0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2) + ret i32 %0 +} + +declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind + +; CHECK: llvm_mips_lsa_test: +; CHECK: lsa {{\$[0-9]+}}, {{\$[0-9]+}}, {{\$[0-9]+}}, 2 +; CHECK: .size llvm_mips_lsa_test + +define i32 @lsa_test(i32 %a, i32 %b) nounwind { +entry: + %0 = shl i32 %b, 2 + %1 = add i32 %a, %0 + ret i32 %1 +} + +; CHECK: lsa_test: +; CHECK: lsa {{\$[0-9]+}}, {{\$[0-9]+}}, {{\$[0-9]+}}, 2 +; CHECK: .size lsa_test |