diff options
28 files changed, 64 insertions, 62 deletions
diff --git a/docs/TableGenFundamentals.html b/docs/TableGenFundamentals.html index 994484f250..ade4bf67df 100644 --- a/docs/TableGenFundamentals.html +++ b/docs/TableGenFundamentals.html @@ -151,7 +151,7 @@ file prints this (at the time of this writing):</p> <b>bit</b> isReMaterializable = 0; <b>bit</b> isPredicable = 0; <b>bit</b> hasDelaySlot = 0; - <b>bit</b> usesCustomDAGSchedInserter = 0; + <b>bit</b> usesCustomInserter = 0; <b>bit</b> hasCtrlDep = 0; <b>bit</b> isNotDuplicable = 0; <b>bit</b> hasSideEffects = 0; diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 4d65b19e2e..edb8582975 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -199,7 +199,7 @@ class Instruction { bit isReMaterializable = 0; // Is this instruction re-materializable? bit isPredicable = 0; // Is this instruction predicable? bit hasDelaySlot = 0; // Does this instruction have an delay slot? - bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help. + bit usesCustomInserter = 0; // Pseudo instr needing special help. bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. diff --git a/include/llvm/Target/TargetInstrDesc.h b/include/llvm/Target/TargetInstrDesc.h index d828a236cd..b0ed0bf0c8 100644 --- a/include/llvm/Target/TargetInstrDesc.h +++ b/include/llvm/Target/TargetInstrDesc.h @@ -109,7 +109,7 @@ namespace TID { UnmodeledSideEffects, Commutable, ConvertibleTo3Addr, - UsesCustomDAGSchedInserter, + UsesCustomInserter, Rematerializable, CheapAsAMove, ExtraSrcRegAllocReq, @@ -416,7 +416,7 @@ public: return Flags & (1 << TID::ConvertibleTo3Addr); } - /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires + /// usesCustomInsertionHook - Return true if this instruction requires /// custom insertion support when the DAG scheduler is inserting it into a /// machine basic block. If this is true for the instruction, it basically /// means that it is a pseudo instruction used at SelectionDAG time that is @@ -424,8 +424,8 @@ public: /// /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method /// is used to insert this into the MachineBasicBlock. - bool usesCustomDAGSchedInsertionHook() const { - return Flags & (1 << TID::UsesCustomDAGSchedInserter); + bool usesCustomInsertionHook() const { + return Flags & (1 << TID::UsesCustomInserter); } /// isRematerializable - Returns true if this instruction is a candidate for diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 84662d2eac..8bc39d0b2c 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -1425,14 +1425,15 @@ public: SelectionDAG &DAG) const; //===--------------------------------------------------------------------===// - // Scheduler hooks + // Instruction Emitting Hooks // // EmitInstrWithCustomInserter - This method should be implemented by targets - // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These + // that mark instructions with the 'usesCustomInserter' flag. These // instructions are special in various ways, which require special support to // insert. The specified MachineInstr is created but not inserted into any - // basic blocks, and the scheduler passes ownership of it to this method. + // basic blocks, and this method is called to expand it into a sequence of + // instructions, potentially also creating new basic blocks and control flow. // When new basic blocks are inserted and the edges from MBB to its successors // are modified, the method should insert pairs of <OldSucc, NewSucc> into the // DenseMap. diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 425f670763..53bebbb44c 100644 --- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -556,7 +556,7 @@ void InstrEmitter::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), cast<MachineSDNode>(Node)->memoperands_end()); - if (II.usesCustomDAGSchedInsertionHook()) { + if (II.usesCustomInsertionHook()) { // Insert this instruction into the basic block using a target // specific inserter which may returns a new basic block. MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 8569e0c45b..6d4562dfed 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -150,16 +150,20 @@ namespace llvm { } // EmitInstrWithCustomInserter - This method should be implemented by targets -// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These +// that mark instructions with the 'usesCustomInserter' flag. These // instructions are special in various ways, which require special support to // insert. The specified MachineInstr is created but not inserted into any -// basic blocks, and the scheduler passes ownership of it to this method. +// basic blocks, and this method is called to expand it into a sequence of +// instructions, potentially also creating new basic blocks and control flow. +// When new basic blocks are inserted and the edges from MBB to its successors +// are modified, the method should insert pairs of <OldSucc, NewSucc> into the +// DenseMap. MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB, DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { #ifndef NDEBUG errs() << "If a target marks an instruction with " - "'usesCustomDAGSchedInserter', it must implement " + "'usesCustomInserter', it must implement " "TargetLowering::EmitInstrWithCustomInserter!"; #endif llvm_unreachable(0); diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index b9be32671e..3823ba6e3a 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -158,7 +158,7 @@ def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, "add\t$dst, $rhs", []>; // Pseudo instruction that will expand into a tSUBspi + a copy. -let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. +let usesCustomInserter = 1 in { // Expanded after instruction selection. def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), NoItinerary, "@ sub\t$dst, $rhs * 4", []>; @@ -168,7 +168,7 @@ def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), let Defs = [CPSR] in def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), NoItinerary, "@ and\t$dst, $rhs", []>; -} // usesCustomDAGSchedInserter +} // usesCustomInserter //===----------------------------------------------------------------------===// // Control Flow Instructions. @@ -617,8 +617,8 @@ def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation. -// Expanded by the scheduler into a branch sequence. -let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler. +// Expanded after instruction selection into a branch sequence. +let usesCustomInserter = 1 in // Expanded after instruction selection. def tMOVCCr_pseudo : PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), NoItinerary, "@ tMOVCCr $cc", diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 9c1c07bf4f..3ee0355584 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -454,14 +454,14 @@ def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), // Pseudo instruction that will expand into a t2SUBrSPi + a copy. -let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. +let usesCustomInserter = 1 in { // Expanded after instruction selection. def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), NoItinerary, "@ sub.w\t$dst, $sp, $imm", []>; def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), NoItinerary, "@ subw\t$dst, $sp, $imm", []>; def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), NoItinerary, "@ sub\t$dst, $sp, $rhs", []>; -} // usesCustomDAGSchedInserter +} // usesCustomInserter //===----------------------------------------------------------------------===// diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index 3b98206e5b..81e1fb7c89 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -164,7 +164,7 @@ def MEMLABEL : PseudoInstAlpha<(outs), (ins s64imm:$i, s64imm:$j, s64imm:$k, s64 "LSMARKER$$$i$$$j$$$k$$$m:", [], s_pseudo>; -let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. +let usesCustomInserter = 1 in { // Expanded after instruction selection. def CAS32 : PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$cmp, GPRC:$swp), "", [(set GPRC:$dst, (atomic_cmp_swap_32 GPRC:$ptr, GPRC:$cmp, GPRC:$swp))], s_pseudo>; def CAS64 : PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$cmp, GPRC:$swp), "", diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td index e202175561..2b50669198 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.td +++ b/lib/Target/MSP430/MSP430InstrInfo.td @@ -108,7 +108,7 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2), [(MSP430callseq_end timm:$amt1, timm:$amt2)]>; } -let usesCustomDAGSchedInserter = 1 in { +let usesCustomInserter = 1 in { def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cc), "# Select8 PSEUDO", [(set GR8:$dst, diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index b6a6d2f5c0..bd61738ecf 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -253,7 +253,7 @@ let hasDelaySlot = 1, Defs=[FCR31] in { // For some explanation, see Select_CC at MipsInstrInfo.td. We also embedd a // condiciton code to enable easy handling by the Custom Inserter. -let usesCustomDAGSchedInserter = 1, Uses=[FCR31] in { +let usesCustomInserter = 1, Uses=[FCR31] in { class PseudoFPSelCC<RegisterClass RC, string asmstr> : MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F, condcode:$cc), asmstr, diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index b9276fe495..46cf43e422 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -417,7 +417,7 @@ def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>; // operation. The solution is to create a Mips pseudo SELECT_CC instruction // (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally // replace it for real supported nodes into EmitInstrWithCustomInserter -let usesCustomDAGSchedInserter = 1 in { +let usesCustomInserter = 1 in { class PseudoSelCC<RegisterClass RC, string asmstr>: MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr, [(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>; diff --git a/lib/Target/PIC16/PIC16InstrInfo.td b/lib/Target/PIC16/PIC16InstrInfo.td index 250ca0a373..5eec6c4e66 100644 --- a/lib/Target/PIC16/PIC16InstrInfo.td +++ b/lib/Target/PIC16/PIC16InstrInfo.td @@ -467,9 +467,9 @@ def br_uncond: ControlFormat<0x0, (outs), (ins brtarget:$dst), "goto $dst", [(br bb:$dst)]>; -// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the -// scheduler into a branch sequence. -let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. +// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after +// instruction selection into a branch sequence. +let usesCustomInserter = 1 in { // Expanded after instruction selection. def SELECT_CC_Int_ICC : Pseudo<(outs GPR:$dst), (ins GPR:$T, GPR:$F, i8imm:$Cond), "; SELECT_CC_Int_ICC PSEUDO!", diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 0f68fb939d..d1e1bd5c1a 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -127,7 +127,7 @@ def : Pat<(PPCnop), (NOP)>; // Atomic operations -let usesCustomDAGSchedInserter = 1 in { +let usesCustomInserter = 1 in { let Uses = [CR0] in { def ATOMIC_LOAD_ADD_I64 : Pseudo< (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index dc5db6ff59..1c7c05e0c4 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -363,9 +363,9 @@ def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), [(set GPRC:$result, (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>; -// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the -// scheduler into a branch sequence. -let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler. +// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after +// instruction selection into a branch sequence. +let usesCustomInserter = 1, // Expanded after instruction selection. PPC970_Single = 1 in { def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F, i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", @@ -539,7 +539,7 @@ def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), PPC970_DGroup_Single; // Atomic operations -let usesCustomDAGSchedInserter = 1 in { +let usesCustomInserter = 1 in { let Uses = [CR0] in { def ATOMIC_LOAD_ADD_I8 : Pseudo< (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 44821b810b..f2f1b96f19 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -238,10 +238,10 @@ let Predicates = [HasNoV9] in { // Only emit these in V8 mode. [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; } -// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the -// scheduler into a branch sequence. This has to handle all permutations of -// selection between i32/f32/f64 on ICC and FCC. -let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. +// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after +// instruction selection into a branch sequence. This has to handle all +// permutations of selection between i32/f32/f64 on ICC and FCC. +let usesCustomInserter = 1 in { // Expanded after instruction selection. def SELECT_CC_Int_ICC : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), "; SELECT_CC_Int_ICC PSEUDO!", diff --git a/lib/Target/SystemZ/SystemZInstrFP.td b/lib/Target/SystemZ/SystemZInstrFP.td index 64e5f254fe..336e20ed89 100644 --- a/lib/Target/SystemZ/SystemZInstrFP.td +++ b/lib/Target/SystemZ/SystemZInstrFP.td @@ -25,7 +25,7 @@ def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>; -let Uses = [PSW], usesCustomDAGSchedInserter = 1 in { +let Uses = [PSW], usesCustomInserter = 1 in { def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc), "# SelectF32 PSEUDO", [(set FP32:$dst, diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 68de580a5a..1891bba2aa 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -74,7 +74,7 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), "#ADJCALLSTACKUP", [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>; -let Uses = [PSW], usesCustomDAGSchedInserter = 1 in { +let Uses = [PSW], usesCustomInserter = 1 in { def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc), "# Select32 PSEUDO", [(set GR32:$dst, diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td index c1b7b8f827..f37a612055 100644 --- a/lib/Target/X86/X86Instr64bit.td +++ b/lib/Target/X86/X86Instr64bit.td @@ -1541,7 +1541,7 @@ def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), } // Atomic exchange, and, or, xor let Constraints = "$val = $dst", Defs = [EFLAGS], - usesCustomDAGSchedInserter = 1 in { + usesCustomInserter = 1 in { def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), "#ATOMAND64 PSEUDO!", [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>; diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td index 7e373730b3..b0b0409ad2 100644 --- a/lib/Target/X86/X86InstrFPStack.td +++ b/lib/Target/X86/X86InstrFPStack.td @@ -69,7 +69,7 @@ def fpimmneg1 : PatLeaf<(fpimm), [{ }]>; // Some 'special' instructions -let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. +let usesCustomInserter = 1 in { // Expanded after instruction selection. def FP32_TO_INT16_IN_MEM : I<0, Pseudo, (outs), (ins i16mem:$dst, RFP32:$src), "##FP32_TO_INT16_IN_MEM PSEUDO!", diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 16b2af71f9..e43d1729b1 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -524,7 +524,7 @@ def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), } // x86-64 va_start lowering magic. -let usesCustomDAGSchedInserter = 1 in +let usesCustomInserter = 1 in def VASTART_SAVE_XMM_REGS : I<0, Pseudo, (outs), (ins GR8:$al, @@ -1129,13 +1129,13 @@ let isTwoAddress = 1 in { // Conditional moves let Uses = [EFLAGS] in { -// X86 doesn't have 8-bit conditional moves. Use a customDAGSchedInserter to +// X86 doesn't have 8-bit conditional moves. Use a customInserter to // emit control flow. An alternative to this is to mark i8 SELECT as Promote, // however that requires promoting the operands, and can induce additional // i8 register pressure. Note that CMOV_GR8 is conservatively considered to // clobber EFLAGS, because if one of the operands is zero, the expansion // could involve an xor. -let usesCustomDAGSchedInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in +let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in def CMOV_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond), "#CMOV_GR8 PSEUDO!", @@ -3667,7 +3667,7 @@ def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), // Atomic exchange, and, or, xor let Constraints = "$val = $dst", Defs = [EFLAGS], - usesCustomDAGSchedInserter = 1 in { + usesCustomInserter = 1 in { def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), "#ATOMAND32 PSEUDO!", [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>; @@ -3736,7 +3736,7 @@ let Constraints = "$val1 = $dst1, $val2 = $dst2", Defs = [EFLAGS, EAX, EBX, ECX, EDX], Uses = [EAX, EBX, ECX, EDX], mayLoad = 1, mayStore = 1, - usesCustomDAGSchedInserter = 1 in { + usesCustomInserter = 1 in { def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), (ins i64mem:$ptr, GR32:$val1, GR32:$val2), "#ATOMAND6432 PSEUDO!", []>; diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td index ce76b4e8b1..500785b990 100644 --- a/lib/Target/X86/X86InstrMMX.td +++ b/lib/Target/X86/X86InstrMMX.td @@ -706,10 +706,9 @@ def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, VR64:$src2)), def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, (bitconvert (load_mmx addr:$src2)))), (MMX_PCMPGTDrm VR64:$src1, addr:$src2)>; -// CMOV* - Used to implement the SELECT DAG operation. Expanded by the -// scheduler into a branch sequence. -// These are expanded by the scheduler. -let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in { +// CMOV* - Used to implement the SELECT DAG operation. Expanded after +// instruction selection into a branch sequence. +let Uses = [EFLAGS], usesCustomInserter = 1 in { def CMOV_V1I64 : I<0, Pseudo, (outs VR64:$dst), (ins VR64:$t, VR64:$f, i8imm:$cond), "#CMOV_V1I64 PSEUDO!", diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 3ab3bff75b..be242a0e5e 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -299,10 +299,9 @@ def palign : PatFrag<(ops node:$lhs, node:$rhs), // SSE scalar FP Instructions //===----------------------------------------------------------------------===// -// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the -// scheduler into a branch sequence. -// These are expanded by the scheduler. -let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in { +// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after +// instruction selection into a branch sequence. +let Uses = [EFLAGS], usesCustomInserter = 1 in { def CMOV_FR32 : I<0, Pseudo, (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond), "#CMOV_FR32 PSEUDO!", @@ -3807,7 +3806,7 @@ let Constraints = "$src1 = $dst" in { } // String/text processing instructions. -let Defs = [EFLAGS], usesCustomDAGSchedInserter = 1 in { +let Defs = [EFLAGS], usesCustomInserter = 1 in { def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3), "#PCMPISTRM128rr PSEUDO!", @@ -3835,7 +3834,7 @@ def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs), } let Defs = [EFLAGS], Uses = [EAX, EDX], - usesCustomDAGSchedInserter = 1 in { + usesCustomInserter = 1 in { def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src3, i8imm:$src5), "#PCMPESTRM128rr PSEUDO!", diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 4b9ea7a491..68e69a2b19 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -357,9 +357,9 @@ def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), "${:comment} STWFI $src, $addr", [(store GRRegs:$src, ADDRspii:$addr)]>; -// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the -// scheduler into a branch sequence. -let usesCustomDAGSchedInserter = 1 in { +// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after +// instruction selection into a branch sequence. +let usesCustomInserter = 1 in { def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), "${:comment} SELECT_CC PSEUDO!", diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp index d421fd07c3..8520d9edee 100644 --- a/utils/TableGen/CodeGenInstruction.cpp +++ b/utils/TableGen/CodeGenInstruction.cpp @@ -94,7 +94,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr) isTerminator = R->getValueAsBit("isTerminator"); isReMaterializable = R->getValueAsBit("isReMaterializable"); hasDelaySlot = R->getValueAsBit("hasDelaySlot"); - usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter"); + usesCustomInserter = R->getValueAsBit("usesCustomInserter"); hasCtrlDep = R->getValueAsBit("hasCtrlDep"); isNotDuplicable = R->getValueAsBit("isNotDuplicable"); hasSideEffects = R->getValueAsBit("hasSideEffects"); diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h index 04506e9d2d..d22ac3e13f 100644 --- a/utils/TableGen/CodeGenInstruction.h +++ b/utils/TableGen/CodeGenInstruction.h @@ -97,7 +97,7 @@ namespace llvm { bool isTerminator; bool isReMaterializable; bool hasDelaySlot; - bool usesCustomDAGSchedInserter; + bool usesCustomInserter; bool isVariadic; bool hasCtrlDep; bool isNotDuplicable; diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index bbb8a18eec..a979cee5c0 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -114,7 +114,7 @@ static unsigned getResultPatternCost(TreePatternNode *P, if (Op->isSubClassOf("Instruction")) { Cost++; CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName()); - if (II.usesCustomDAGSchedInserter) + if (II.usesCustomInserter) Cost += 10; } for (unsigned i = 0, e = P->getNumChildren(); i != e; ++i) diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index 3a104ea358..adb98fb958 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -275,8 +275,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)"; if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)"; if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)"; - if (Inst.usesCustomDAGSchedInserter) - OS << "|(1<<TID::UsesCustomDAGSchedInserter)"; + if (Inst.usesCustomInserter) OS << "|(1<<TID::UsesCustomInserter)"; if (Inst.isVariadic) OS << "|(1<<TID::Variadic)"; if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)"; if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)"; |