diff options
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrInfo.td | 30 | ||||
| -rw-r--r-- | lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 16 | ||||
| -rw-r--r-- | lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp | 11 | ||||
| -rw-r--r-- | test/MC/Disassembler/AArch64/a64-ignored-fields.txt | 8 |
4 files changed, 38 insertions, 27 deletions
diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td index 78c4ad16d7..319ec97cfc 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.td +++ b/lib/Target/AArch64/AArch64InstrInfo.td @@ -1945,43 +1945,41 @@ def fpz32 : Operand<f32>, ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> { let ParserMatchClass = fpzero_asmoperand; let PrintMethod = "printFPZeroOperand"; + let DecoderMethod = "DecodeFPZeroOperand"; } def fpz64 : Operand<f64>, ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> { let ParserMatchClass = fpzero_asmoperand; let PrintMethod = "printFPZeroOperand"; + let DecoderMethod = "DecodeFPZeroOperand"; } -multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, string asmop2, - dag pattern> { +multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> { def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0}, - (outs), ins, !strconcat("fcmp\t$Rn, ", asmop2), - [pattern], NoItinerary> { + (outs), ins, "fcmp\t$Rn, $Rm", [pattern], + NoItinerary> { let Defs = [NZCV]; } def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0}, - (outs), ins, !strconcat("fcmpe\t$Rn, ", asmop2), - [], NoItinerary> { + (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> { let Defs = [NZCV]; } } -defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm), "$Rm", +defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm), (set NZCV, (A64cmp (f32 FPR32:$Rn), FPR32:$Rm))>; -defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm), "$Rm", +defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm), (set NZCV, (A64cmp (f64 FPR64:$Rn), FPR64:$Rm))>; -// What would be Rm should be written as 0, but anything is valid for -// disassembly so we can't set the bits -let PostEncoderMethod = "fixFCMPImm" in { - defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Imm), "$Imm", - (set NZCV, (A64cmp (f32 FPR32:$Rn), fpz32:$Imm))>; +// What would be Rm should be written as 0; note that even though it's called +// "$Rm" here to fit in with the InstrFormats, it's actually an immediate. +defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm), + (set NZCV, (A64cmp (f32 FPR32:$Rn), fpz32:$Rm))>; - defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Imm), "$Imm", - (set NZCV, (A64cmp (f64 FPR64:$Rn), fpz64:$Imm))>; -} +defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm), + (set NZCV, (A64cmp (f64 FPR64:$Rn), fpz64:$Rm))>; //===----------------------------------------------------------------------===// diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index eba76667e2..12c1b8f4c8 100644 --- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -106,6 +106,11 @@ static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, + unsigned RmBits, + uint64_t Address, + const void *Decoder); + template<int RegWidth> static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, unsigned FullImm, @@ -381,6 +386,17 @@ static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, + unsigned RmBits, + uint64_t Address, + const void *Decoder) { + // Any bits are valid in the instruction (they're architecturally ignored), + // but a code generator should insert 0. + Inst.addOperand(MCOperand::CreateImm(0)); + return MCDisassembler::Success; +} + + template<int RegWidth> static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp index 756e037e93..a5c591eee8 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp @@ -106,8 +106,6 @@ public: void EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const; - unsigned fixFCMPImm(const MCInst &MI, unsigned EncodedValue) const; - template<int hasRs, int hasRt2> unsigned fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue) const; @@ -423,15 +421,6 @@ AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, return Result | getAddressWithFixup(UImm16MO, requestedFixup, Fixups); } -unsigned AArch64MCCodeEmitter::fixFCMPImm(const MCInst &MI, - unsigned EncodedValue) const { - // For FCMP[E] Rn, #0.0, the Rm field has a canonical representation - // with 0s, but is architecturally ignored - EncodedValue &= ~0x1f0000u; - - return EncodedValue; -} - template<int hasRs, int hasRt2> unsigned AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue) const { diff --git a/test/MC/Disassembler/AArch64/a64-ignored-fields.txt b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt new file mode 100644 index 0000000000..966530d36a --- /dev/null +++ b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt @@ -0,0 +1,8 @@ +# RUN: llvm-mc -triple=aarch64 -disassemble -show-encoding < %s | FileCheck %s + +# The "Rm" bits are ignored, but the canonical representation has them filled +# with 0s. This is what we should produce even if the input bit-pattern had +# something else there. + +# CHECK: fcmp s31, #0.0 // encoding: [0xe8,0x23,0x20,0x1e] +0xe8 0x23 0x33 0x1e |