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-rw-r--r--include/llvm/CodeGen/ScheduleDAG.h4
-rw-r--r--include/llvm/CodeGen/SelectionDAGISel.h5
-rw-r--r--include/llvm/Support/Timer.h2
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAG.cpp11
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp7
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp7
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp49
-rw-r--r--lib/Support/Timer.cpp36
8 files changed, 82 insertions, 39 deletions
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index ed7801fbfc..0225b1231e 100644
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -265,7 +265,7 @@ namespace llvm {
/// Run - perform scheduling.
///
- MachineBasicBlock *Run();
+ void Run();
/// isPassiveNode - Return true if the node is a non-scheduled leaf.
///
@@ -336,7 +336,7 @@ namespace llvm {
///
void EmitNoop();
- void EmitSchedule();
+ MachineBasicBlock *EmitSchedule();
void dumpSchedule() const;
diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index e0b26b926b..72a836f55b 100644
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -30,6 +30,7 @@ namespace llvm {
class FunctionLoweringInfo;
class HazardRecognizer;
class CollectorMetadata;
+ class ScheduleDAG;
/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
/// pattern-matching instruction selectors.
@@ -191,9 +192,9 @@ private:
void ComputeLiveOutVRegInfo(SelectionDAG &DAG);
- /// Pick a safe ordering and emit instructions for each target node in the
+ /// Pick a safe ordering for instructions for each target node in the
/// graph.
- void ScheduleAndEmitDAG(SelectionDAG &DAG);
+ ScheduleDAG *Schedule(SelectionDAG &DAG);
/// SwitchCases - Vector of CaseBlock structures used to communicate
/// SwitchInst code generation information.
diff --git a/include/llvm/Support/Timer.h b/include/llvm/Support/Timer.h
index 4164ddc891..b9882a9708 100644
--- a/include/llvm/Support/Timer.h
+++ b/include/llvm/Support/Timer.h
@@ -132,6 +132,8 @@ public:
///
struct NamedRegionTimer : public TimeRegion {
explicit NamedRegionTimer(const std::string &Name);
+ explicit NamedRegionTimer(const std::string &Name,
+ const std::string &GroupName);
};
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 02f20f919e..982bbab3cb 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -1082,7 +1082,7 @@ void ScheduleDAG::EmitLiveInCopies(MachineBasicBlock *MBB) {
}
/// EmitSchedule - Emit the machine code in scheduled order.
-void ScheduleDAG::EmitSchedule() {
+MachineBasicBlock *ScheduleDAG::EmitSchedule() {
bool isEntryBB = &MF->front() == BB;
if (isEntryBB && !SchedLiveInCopies) {
@@ -1118,6 +1118,8 @@ void ScheduleDAG::EmitSchedule() {
if (isEntryBB && SchedLiveInCopies)
EmitLiveInCopies(MF->begin());
+
+ return BB;
}
/// dump - dump the schedule.
@@ -1133,9 +1135,12 @@ void ScheduleDAG::dumpSchedule() const {
/// Run - perform scheduling.
///
-MachineBasicBlock *ScheduleDAG::Run() {
+void ScheduleDAG::Run() {
Schedule();
- return BB;
+
+ DOUT << "*** Final schedule ***\n";
+ DEBUG(dumpSchedule());
+ DOUT << "\n";
}
/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
index 8a1dade30b..39aadd5279 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -99,13 +99,6 @@ void ScheduleDAGList::Schedule() {
ListScheduleTopDown();
AvailableQueue->releaseState();
-
- DOUT << "*** Final schedule ***\n";
- DEBUG(dumpSchedule());
- DOUT << "\n";
-
- // Emit in scheduled order
- EmitSchedule();
}
//===----------------------------------------------------------------------===//
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 287e8c5b0e..098b7996d4 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -204,13 +204,6 @@ void ScheduleDAGRRList::Schedule() {
if (!Fast)
CommuteNodesToReducePressure();
-
- DOUT << "*** Final schedule ***\n";
- DEBUG(dumpSchedule());
- DOUT << "\n";
-
- // Emit in scheduled order
- EmitSchedule();
}
/// CommuteNodesToReducePressure - If a node is two-address and commutable, and
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index b4b81cd4f1..bf68040c97 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -5284,10 +5284,11 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
DOUT << "Lowered selection DAG:\n";
DEBUG(DAG.dump());
+ std::string GroupName = "Instruction Selection and Scheduling";
// Run the DAG combiner in pre-legalize mode.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("DAG Combining 1");
+ NamedRegionTimer T("DAG Combining 1", GroupName);
DAG.Combine(false, *AA);
} else {
DAG.Combine(false, *AA);
@@ -5304,7 +5305,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
}
if (TimePassesIsEnabled) {
- NamedRegionTimer T("DAG Legalization");
+ NamedRegionTimer T("DAG Legalization", GroupName);
DAG.Legalize();
} else {
DAG.Legalize();
@@ -5315,7 +5316,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
// Run the DAG combiner in post-legalize mode.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("DAG Combining 2");
+ NamedRegionTimer T("DAG Combining 2", GroupName);
DAG.Combine(true, *AA);
} else {
DAG.Combine(true, *AA);
@@ -5332,24 +5333,41 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
// Third, instruction select all of the operations to machine code, adding the
// code to the MachineBasicBlock.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("Instruction Selection");
+ NamedRegionTimer T("Instruction Selection", GroupName);
InstructionSelect(DAG);
} else {
InstructionSelect(DAG);
}
+ // Schedule machine code.
+ ScheduleDAG *Scheduler;
+ if (TimePassesIsEnabled) {
+ NamedRegionTimer T("Instruction Scheduling", GroupName);
+ Scheduler = Schedule(DAG);
+ } else {
+ Scheduler = Schedule(DAG);
+ }
+
// Emit machine code to BB. This can change 'BB' to the last block being
// inserted into.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("Instruction Scheduling");
- ScheduleAndEmitDAG(DAG);
+ NamedRegionTimer T("Instruction Creation", GroupName);
+ BB = Scheduler->EmitSchedule();
} else {
- ScheduleAndEmitDAG(DAG);
+ BB = Scheduler->EmitSchedule();
+ }
+
+ // Free the scheduler state.
+ if (TimePassesIsEnabled) {
+ NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
+ delete Scheduler;
+ } else {
+ delete Scheduler;
}
// Perform target specific isel post processing.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("Instruction Selection Post Processing");
+ NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
InstructionSelectPostProcessing(DAG);
} else {
InstructionSelectPostProcessing(DAG);
@@ -5597,10 +5615,10 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
}
-//===----------------------------------------------------------------------===//
-/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
+/// Schedule - Pick a safe ordering for instructions for each
/// target node in the graph.
-void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
+///
+ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
if (ViewSchedDAGs) DAG.viewGraph();
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
@@ -5610,12 +5628,11 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
RegisterScheduler::setDefault(Ctor);
}
- ScheduleDAG *SL = Ctor(this, &DAG, BB, FastISel);
- BB = SL->Run();
-
- if (ViewSUnitDAGs) SL->viewGraph();
+ ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
+ Scheduler->Run();
- delete SL;
+ if (ViewSUnitDAGs) Scheduler->viewGraph();
+ return Scheduler;
}
diff --git a/lib/Support/Timer.cpp b/lib/Support/Timer.cpp
index 29fd00c0a3..3c8879bd06 100644
--- a/lib/Support/Timer.cpp
+++ b/lib/Support/Timer.cpp
@@ -182,19 +182,51 @@ void Timer::addPeakMemoryMeasurement() {
// NamedRegionTimer Implementation
//===----------------------------------------------------------------------===//
-static ManagedStatic<std::map<std::string, Timer> > NamedTimers;
+namespace {
+
+typedef std::map<std::string, Timer> Name2Timer;
+typedef std::map<std::string, std::pair<TimerGroup, Name2Timer> > Name2Pair;
+
+}
+
+static ManagedStatic<Name2Timer> NamedTimers;
+
+static ManagedStatic<Name2Pair> NamedGroupedTimers;
static Timer &getNamedRegionTimer(const std::string &Name) {
- std::map<std::string, Timer>::iterator I = NamedTimers->find(Name);
+ Name2Timer::iterator I = NamedTimers->find(Name);
if (I != NamedTimers->end())
return I->second;
return NamedTimers->insert(I, std::make_pair(Name, Timer(Name)))->second;
}
+static Timer &getNamedRegionTimer(const std::string &Name,
+ const std::string &GroupName) {
+
+ Name2Pair::iterator I = NamedGroupedTimers->find(GroupName);
+ if (I == NamedGroupedTimers->end()) {
+ TimerGroup TG(GroupName);
+ std::pair<TimerGroup, Name2Timer> Pair(TG, Name2Timer());
+ I = NamedGroupedTimers->insert(I, std::make_pair(GroupName, Pair));
+ }
+
+ Name2Timer::iterator J = I->second.second.find(Name);
+ if (J == I->second.second.end())
+ J = I->second.second.insert(J,
+ std::make_pair(Name,
+ Timer(Name,
+ I->second.first)));
+
+ return J->second;
+}
+
NamedRegionTimer::NamedRegionTimer(const std::string &Name)
: TimeRegion(getNamedRegionTimer(Name)) {}
+NamedRegionTimer::NamedRegionTimer(const std::string &Name,
+ const std::string &GroupName)
+ : TimeRegion(getNamedRegionTimer(Name, GroupName)) {}
//===----------------------------------------------------------------------===//
// TimerGroup Implementation
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-14 14:06:43 +0000