diff options
| -rw-r--r-- | lib/Target/ARM/ARMAsmPrinter.cpp | 22 | ||||
| -rw-r--r-- | lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp | 1 | ||||
| -rw-r--r-- | test/CodeGen/ARM/build-attributes.ll | 4 | ||||
| -rw-r--r-- | test/MC/ARM/directive-arch-armv6-m.s | 6 |
4 files changed, 18 insertions, 15 deletions
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 84d1476d04..c4303f0300 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -630,15 +630,19 @@ void ARMAsmPrinter::emitAttributes() { ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, Subtarget)); - if (Subtarget->isAClass()) { - ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile, - ARMBuildAttrs::ApplicationProfile); - } else if (Subtarget->isRClass()) { - ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile, - ARMBuildAttrs::RealTimeProfile); - } else if (Subtarget->isMClass()){ - ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile, - ARMBuildAttrs::MicroControllerProfile); + // Tag_CPU_arch_profile must have the default value of 0 when "Architecture + // profile is not applicable (e.g. pre v7, or cross-profile code)". + if (Subtarget->hasV7Ops()) { + if (Subtarget->isAClass()) { + ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile, + ARMBuildAttrs::ApplicationProfile); + } else if (Subtarget->isRClass()) { + ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile, + ARMBuildAttrs::RealTimeProfile); + } else if (Subtarget->isMClass()) { + ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile, + ARMBuildAttrs::MicroControllerProfile); + } } ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ? diff --git a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp index fd9151f2d2..ec3c5fe842 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -692,7 +692,6 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() { break; case ARM::ARMV6M: - setAttributeItem(CPU_arch_profile, MicroControllerProfile, false); setAttributeItem(THUMB_ISA_use, Allowed, false); break; diff --git a/test/CodeGen/ARM/build-attributes.ll b/test/CodeGen/ARM/build-attributes.ll index faf89728a8..ce7a31f3dc 100644 --- a/test/CodeGen/ARM/build-attributes.ll +++ b/test/CodeGen/ARM/build-attributes.ll @@ -43,7 +43,7 @@ ; V6-NOT: .eabi_attribute 68 ; V6M: .eabi_attribute 6, 12 -; V6M: .eabi_attribute 7, 77 +; V6M-NOT: .eabi_attribute 7 ; V6M: .eabi_attribute 8, 0 ; V6M: .eabi_attribute 9, 1 ; V6M: .eabi_attribute 24, 1 @@ -333,7 +333,7 @@ ; CORTEX-M0: .cpu cortex-m0 ; CORTEX-M0: .eabi_attribute 6, 12 -; CORTEX-M0: .eabi_attribute 7, 77 +; CORTEX-M0-NOT: .eabi_attribute 7 ; CORTEX-M0: .eabi_attribute 8, 0 ; CORTEX-M0: .eabi_attribute 9, 1 ; CORTEX-M0: .eabi_attribute 24, 1 diff --git a/test/MC/ARM/directive-arch-armv6-m.s b/test/MC/ARM/directive-arch-armv6-m.s index 5a28905b6a..fc70827903 100644 --- a/test/MC/ARM/directive-arch-armv6-m.s +++ b/test/MC/ARM/directive-arch-armv6-m.s @@ -19,12 +19,12 @@ @ CHECK-OBJ: ] @ CHECK-OBJ: Address: 0x0 @ CHECK-OBJ: Offset: 0x34 -@ CHECK-OBJ: Size: 27 +@ CHECK-OBJ: Size: 25 @ CHECK-OBJ: Link: 0 @ CHECK-OBJ: Info: 0 @ CHECK-OBJ: AddressAlignment: 1 @ CHECK-OBJ: EntrySize: 0 @ CHECK-OBJ: SectionData ( -@ CHECK-OBJ: 0000: 411A0000 00616561 62690001 10000000 |A....aeabi......| -@ CHECK-OBJ: 0010: 05362D4D 00060B07 4D0901 |.6-M....M..| +@ CHECK-OBJ: 0000: 41180000 00616561 62690001 0E000000 |A....aeabi......| +@ CHECK-OBJ: 0010: 05362D4D 00060B09 01 |.6-M.....| @ CHECK-OBJ: ) |