diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 11 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/vsx.ll | 18 |
3 files changed, 28 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index e09725d59d..87639247e2 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -7960,7 +7960,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty); if (ISD::isNON_EXTLoad(N) && VT.isVector() && TM.getSubtarget<PPCSubtarget>().hasAltivec() && - // FIXME: Update this for VSX! (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || VT == MVT::v4f32) && LD->getAlignment() < ABIAlignment) { @@ -8716,8 +8715,14 @@ bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, if (!VT.isSimple()) return false; - if (VT.getSimpleVT().isVector()) - return false; + if (VT.getSimpleVT().isVector()) { + if (PPCSubTarget.hasVSX()) { + if (VT != MVT::v2f64 && VT != MVT::v2i64) + return false; + } else { + return false; + } + } if (VT == MVT::ppcf128) return false; diff --git a/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 2491a9e539..a915b04fa5 100644 --- a/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -244,6 +244,8 @@ unsigned PPCTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, // Each load/store unit costs 1. unsigned Cost = LT.first * 1; + // FIXME: Update this for VSX loads/stores that support unaligned access. + // PPC in general does not support unaligned loads and stores. They'll need // to be decomposed based on the alignment factor. unsigned SrcBytes = LT.second.getStoreSize(); diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll index d2f8bb8ee5..36848427a5 100644 --- a/test/CodeGen/PowerPC/vsx.ll +++ b/test/CodeGen/PowerPC/vsx.ll @@ -314,6 +314,24 @@ define void @test29(<2 x double>* %a, <2 x double> %b) { ; CHECK: blr } +define <2 x double> @test28u(<2 x double>* %a) { + %v = load <2 x double>* %a, align 8 + ret <2 x double> %v + +; CHECK-LABEL: @test28u +; CHECK: lxvd2x 34, 0, 3 +; CHECK: blr +} + +define void @test29u(<2 x double>* %a, <2 x double> %b) { + store <2 x double> %b, <2 x double>* %a, align 8 + ret void + +; CHECK-LABEL: @test29u +; CHECK: stxvd2x 34, 0, 3 +; CHECK: blr +} + define <2 x i64> @test30(<2 x i64>* %a) { %v = load <2 x i64>* %a, align 16 ret <2 x i64> %v |