diff options
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrFormats.td | 35 | ||||
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.td | 4 | ||||
| -rw-r--r-- | test/CodeGen/SystemZ/int-add-14.ll | 67 | ||||
| -rw-r--r-- | test/CodeGen/SystemZ/int-add-15.ll | 67 | ||||
| -rw-r--r-- | test/MC/Disassembler/SystemZ/insns.txt | 30 | ||||
| -rw-r--r-- | test/MC/SystemZ/insn-bad-z196.s | 23 | ||||
| -rw-r--r-- | test/MC/SystemZ/insn-bad.s | 10 | ||||
| -rw-r--r-- | test/MC/SystemZ/insn-good-z196.s | 36 |
8 files changed, 270 insertions, 2 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrFormats.td b/lib/Target/SystemZ/SystemZInstrFormats.td index f099975628..9257a6a03f 100644 --- a/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/lib/Target/SystemZ/SystemZInstrFormats.td @@ -181,6 +181,23 @@ class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> let Inst{7-0} = op{7-0}; } +class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<4> R1; + bits<4> R3; + bits<16> I2; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = R1; + let Inst{35-32} = R3; + let Inst{31-16} = I2; + let Inst{15-8} = 0; + let Inst{7-0} = op{7-0}; +} + class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; @@ -768,6 +785,24 @@ class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, let DisableEncoding = "$R1src"; } +class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator, + RegisterOperand cls, Immediate imm> + : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2), + mnemonic#"\t$R1, $R3, $I2", + [(set cls:$R1, (operator cls:$R3, imm:$I2))]>; + +multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2, + SDPatternOperator operator, RegisterOperand cls, + Immediate imm> { + let NumOpsKey = mnemonic in { + let NumOpsValue = "3" in + def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>, + Requires<[FeatureDistinctOps]>; + let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in + def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>; + } +} + class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, RegisterOperand cls, Immediate imm> : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index fe2b5367fc..5ffb86b32e 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -541,8 +541,8 @@ let Defs = [CC] in { def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>; // Addition of signed 16-bit immediates. - def AHI : BinaryRI<"ahi", 0xA7A, add, GR32, imm32sx16>; - def AGHI : BinaryRI<"aghi", 0xA7B, add, GR64, imm64sx16>; + defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>; + defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>; // Addition of signed 32-bit immediates. def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>; diff --git a/test/CodeGen/SystemZ/int-add-14.ll b/test/CodeGen/SystemZ/int-add-14.ll new file mode 100644 index 0000000000..07323789c3 --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-14.ll @@ -0,0 +1,67 @@ +; Test 32-bit addition in which the second operand is constant and in which +; three-operand forms are available. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s + +; Check additions of 1. +define i32 @f1(i32 %a, i32 %b) { +; CHECK-LABEL: f1: +; CHECK: ahik %r2, %r3, 1 +; CHECK: br %r14 + %add = add i32 %b, 1 + ret i32 %add +} + +; Check the high end of the AHIK range. +define i32 @f2(i32 %a, i32 %b) { +; CHECK-LABEL: f2: +; CHECK: ahik %r2, %r3, 32767 +; CHECK: br %r14 + %add = add i32 %b, 32767 + ret i32 %add +} + +; Check the next value up, which must use AFI instead. +define i32 @f3(i32 %a, i32 %b) { +; CHECK-LABEL: f3: +; CHECK: afi {{%r[0-5]}}, 32768 +; CHECK: br %r14 + %add = add i32 %b, 32768 + ret i32 %add +} + +; Check the high end of the negative AHIK range. +define i32 @f4(i32 %a, i32 %b) { +; CHECK-LABEL: f4: +; CHECK: ahik %r2, %r3, -1 +; CHECK: br %r14 + %add = add i32 %b, -1 + ret i32 %add +} + +; Check the low end of the AHIK range. +define i32 @f5(i32 %a, i32 %b) { +; CHECK-LABEL: f5: +; CHECK: ahik %r2, %r3, -32768 +; CHECK: br %r14 + %add = add i32 %b, -32768 + ret i32 %add +} + +; Check the next value down, which must use AFI instead. +define i32 @f6(i32 %a, i32 %b) { +; CHECK-LABEL: f6: +; CHECK: afi {{%r[0-5]}}, -32769 +; CHECK: br %r14 + %add = add i32 %b, -32769 + ret i32 %add +} + +; Check that AHI is still used in obvious cases. +define i32 @f7(i32 %a) { +; CHECK-LABEL: f7: +; CHECK: ahi %r2, 1 +; CHECK: br %r14 + %add = add i32 %a, 1 + ret i32 %add +} diff --git a/test/CodeGen/SystemZ/int-add-15.ll b/test/CodeGen/SystemZ/int-add-15.ll new file mode 100644 index 0000000000..041ec19142 --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-15.ll @@ -0,0 +1,67 @@ +; Test 64-bit addition in which the second operand is constant and in which +; three-operand forms are available. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s + +; Check additions of 1. +define i64 @f1(i64 %a, i64 %b) { +; CHECK-LABEL: f1: +; CHECK: {{aghik %r2, %r3, 1|la %r2, 1\(%r3\)}} +; CHECK: br %r14 + %add = add i64 %b, 1 + ret i64 %add +} + +; Check the high end of the AGHIK range. +define i64 @f2(i64 %a, i64 %b) { +; CHECK-LABEL: f2: +; CHECK: aghik %r2, %r3, 32767 +; CHECK: br %r14 + %add = add i64 %b, 32767 + ret i64 %add +} + +; Check the next value up, which must use AGFI instead. +define i64 @f3(i64 %a, i64 %b) { +; CHECK-LABEL: f3: +; CHECK: {{agfi %r[0-5], 32768|lay %r2, 32768\(%r3\)}} +; CHECK: br %r14 + %add = add i64 %b, 32768 + ret i64 %add +} + +; Check the high end of the negative AGHIK range. +define i64 @f4(i64 %a, i64 %b) { +; CHECK-LABEL: f4: +; CHECK: aghik %r2, %r3, -1 +; CHECK: br %r14 + %add = add i64 %b, -1 + ret i64 %add +} + +; Check the low end of the AGHIK range. +define i64 @f5(i64 %a, i64 %b) { +; CHECK-LABEL: f5: +; CHECK: aghik %r2, %r3, -32768 +; CHECK: br %r14 + %add = add i64 %b, -32768 + ret i64 %add +} + +; Check the next value down, which must use AGFI instead. +define i64 @f6(i64 %a, i64 %b) { +; CHECK-LABEL: f6: +; CHECK: {{agfi %r[0-5], -32769|lay %r2, -32769\(%r3\)}} +; CHECK: br %r14 + %add = add i64 %b, -32769 + ret i64 %add +} + +; Check that AGHI is still used in obvious cases. +define i64 @f7(i64 %a) { +; CHECK-LABEL: f7: +; CHECK: aghi %r2, 32000 +; CHECK: br %r14 + %add = add i64 %a, 32000 + ret i64 %add +} diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt index 4c0755ae70..e91be56b5c 100644 --- a/test/MC/Disassembler/SystemZ/insns.txt +++ b/test/MC/Disassembler/SystemZ/insns.txt @@ -163,6 +163,21 @@ # CHECK: aghi %r15, 0 0xa7 0xfb 0x00 0x00 +# CHECK: aghik %r0, %r1, -32768 +0xec 0x01 0x80 0x00 0x00 0xd9 + +# CHECK: aghik %r2, %r3, -1 +0xec 0x23 0xff 0xff 0x00 0xd9 + +# CHECK: aghik %r4, %r5, 0 +0xec 0x45 0x00 0x00 0x00 0xd9 + +# CHECK: aghik %r6, %r7, 1 +0xec 0x67 0x00 0x01 0x00 0xd9 + +# CHECK: aghik %r8, %r15, 32767 +0xec 0x8f 0x7f 0xff 0x00 0xd9 + # CHECK: agr %r0, %r0 0xb9 0x08 0x00 0x00 @@ -268,6 +283,21 @@ # CHECK: ahi %r15, 0 0xa7 0xfa 0x00 0x00 +# CHECK: ahik %r0, %r1, -32768 +0xec 0x01 0x80 0x00 0x00 0xd8 + +# CHECK: ahik %r2, %r3, -1 +0xec 0x23 0xff 0xff 0x00 0xd8 + +# CHECK: ahik %r4, %r5, 0 +0xec 0x45 0x00 0x00 0x00 0xd8 + +# CHECK: ahik %r6, %r7, 1 +0xec 0x67 0x00 0x01 0x00 0xd8 + +# CHECK: ahik %r8, %r15, 32767 +0xec 0x8f 0x7f 0xff 0x00 0xd8 + # CHECK: ah %r0, 0 0x4a 0x00 0x00 0x00 diff --git a/test/MC/SystemZ/insn-bad-z196.s b/test/MC/SystemZ/insn-bad-z196.s index 0124401caa..b4dc529531 100644 --- a/test/MC/SystemZ/insn-bad-z196.s +++ b/test/MC/SystemZ/insn-bad-z196.s @@ -1,6 +1,29 @@ # For z196 only. # RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=z196 < %s 2> %t # RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: aghik %r0, %r1, -32769 +#CHECK: error: invalid operand +#CHECK: aghik %r0, %r1, 32768 +#CHECK: error: invalid operand +#CHECK: aghik %r0, %r1, foo + + aghik %r0, %r1, -32769 + aghik %r0, %r1, 32768 + aghik %r0, %r1, foo + +#CHECK: error: invalid operand +#CHECK: ahik %r0, %r1, -32769 +#CHECK: error: invalid operand +#CHECK: ahik %r0, %r1, 32768 +#CHECK: error: invalid operand +#CHECK: ahik %r0, %r1, foo + + ahik %r0, %r1, -32769 + ahik %r0, %r1, 32768 + ahik %r0, %r1, foo + #CHECK: error: invalid operand #CHECK: sllk %r0,%r0,-524289 #CHECK: error: invalid operand diff --git a/test/MC/SystemZ/insn-bad.s b/test/MC/SystemZ/insn-bad.s index 038f745a02..f0a8e414b1 100644 --- a/test/MC/SystemZ/insn-bad.s +++ b/test/MC/SystemZ/insn-bad.s @@ -70,6 +70,11 @@ aghi %r0, foo #CHECK: error: {{(instruction requires: distinct-ops)?}} +#CHECK: aghik %r1, %r2, 3 + + aghik %r1, %r2, 3 + +#CHECK: error: {{(instruction requires: distinct-ops)?}} #CHECK: agrk %r2,%r3,%r4 agrk %r2,%r3,%r4 @@ -110,6 +115,11 @@ ahi %r0, 32768 ahi %r0, foo +#CHECK: error: {{(instruction requires: distinct-ops)?}} +#CHECK: ahik %r1, %r2, 3 + + ahik %r1, %r2, 3 + #CHECK: error: invalid operand #CHECK: ahy %r0, -524289 #CHECK: error: invalid operand diff --git a/test/MC/SystemZ/insn-good-z196.s b/test/MC/SystemZ/insn-good-z196.s index 6e3a6a0ea0..6bfb7e862b 100644 --- a/test/MC/SystemZ/insn-good-z196.s +++ b/test/MC/SystemZ/insn-good-z196.s @@ -1,6 +1,24 @@ # For z196 and above. # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z196 -show-encoding %s | FileCheck %s +#CHECK: aghik %r0, %r0, -32768 # encoding: [0xec,0x00,0x80,0x00,0x00,0xd9] +#CHECK: aghik %r0, %r0, -1 # encoding: [0xec,0x00,0xff,0xff,0x00,0xd9] +#CHECK: aghik %r0, %r0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0xd9] +#CHECK: aghik %r0, %r0, 1 # encoding: [0xec,0x00,0x00,0x01,0x00,0xd9] +#CHECK: aghik %r0, %r0, 32767 # encoding: [0xec,0x00,0x7f,0xff,0x00,0xd9] +#CHECK: aghik %r0, %r15, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0xd9] +#CHECK: aghik %r15, %r0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0xd9] +#CHECK: aghik %r7, %r8, -16 # encoding: [0xec,0x78,0xff,0xf0,0x00,0xd9] + + aghik %r0, %r0, -32768 + aghik %r0, %r0, -1 + aghik %r0, %r0, 0 + aghik %r0, %r0, 1 + aghik %r0, %r0, 32767 + aghik %r0, %r15, 0 + aghik %r15, %r0, 0 + aghik %r7, %r8, -16 + #CHECK: agrk %r0, %r0, %r0 # encoding: [0xb9,0xe8,0x00,0x00] #CHECK: agrk %r0, %r0, %r15 # encoding: [0xb9,0xe8,0xf0,0x00] #CHECK: agrk %r0, %r15, %r0 # encoding: [0xb9,0xe8,0x00,0x0f] @@ -13,6 +31,24 @@ agrk %r15,%r0,%r0 agrk %r7,%r8,%r9 +#CHECK: ahik %r0, %r0, -32768 # encoding: [0xec,0x00,0x80,0x00,0x00,0xd8] +#CHECK: ahik %r0, %r0, -1 # encoding: [0xec,0x00,0xff,0xff,0x00,0xd8] +#CHECK: ahik %r0, %r0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0xd8] +#CHECK: ahik %r0, %r0, 1 # encoding: [0xec,0x00,0x00,0x01,0x00,0xd8] +#CHECK: ahik %r0, %r0, 32767 # encoding: [0xec,0x00,0x7f,0xff,0x00,0xd8] +#CHECK: ahik %r0, %r15, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0xd8] +#CHECK: ahik %r15, %r0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0xd8] +#CHECK: ahik %r7, %r8, -16 # encoding: [0xec,0x78,0xff,0xf0,0x00,0xd8] + + ahik %r0, %r0, -32768 + ahik %r0, %r0, -1 + ahik %r0, %r0, 0 + ahik %r0, %r0, 1 + ahik %r0, %r0, 32767 + ahik %r0, %r15, 0 + ahik %r15, %r0, 0 + ahik %r7, %r8, -16 + #CHECK: ark %r0, %r0, %r0 # encoding: [0xb9,0xf8,0x00,0x00] #CHECK: ark %r0, %r0, %r15 # encoding: [0xb9,0xf8,0xf0,0x00] #CHECK: ark %r0, %r15, %r0 # encoding: [0xb9,0xf8,0x00,0x0f] |