diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/xor.ll | 14 |
2 files changed, 15 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8d6eab7c7b..23e33d4ed2 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3583,7 +3583,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) { } // fold (xor (and x, y), y) -> (and (not x), y) if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && - N0->getOperand(1) == N1) { + N0->getOperand(1) == N1 && isTypeLegal(VT.getScalarType())) { SDValue X = N0->getOperand(0); SDValue NotX = DAG.getNOT(SDLoc(X), X, VT); AddToWorkList(NotX.getNode()); diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll index b56ce0f52c..be2ea525b1 100644 --- a/test/CodeGen/X86/xor.ll +++ b/test/CodeGen/X86/xor.ll @@ -165,3 +165,17 @@ define <4 x i32> @test10(<4 x i32> %a) nounwind { ; X32-LABEL: test10: ; X32: andnps } + +define i32 @PR17487(i1 %tobool) { + %tmp = insertelement <2 x i1> undef, i1 %tobool, i32 1 + %tmp1 = zext <2 x i1> %tmp to <2 x i64> + %tmp2 = xor <2 x i64> %tmp1, <i64 1, i64 1> + %tmp3 = extractelement <2 x i64> %tmp2, i32 1 + %add = add nsw i64 0, %tmp3 + %cmp6 = icmp ne i64 %add, 1 + %conv7 = zext i1 %cmp6 to i32 + ret i32 %conv7 + +; X64-LABEL: PR17487: +; X64: andn +} |