diff options
| -rw-r--r-- | docs/WritingAnLLVMBackend.html | 3 | ||||
| -rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 20 | ||||
| -rw-r--r-- | include/llvm/Target/TargetOpcodes.h | 3 | ||||
| -rw-r--r-- | lib/CodeGen/TargetInstrInfoImpl.cpp | 17 | ||||
| -rw-r--r-- | test/CodeGen/Blackfin/cmp64.ll | 4 | ||||
| -rw-r--r-- | test/TableGen/TargetInstrInfo.td | 3 |
6 files changed, 9 insertions, 41 deletions
diff --git a/docs/WritingAnLLVMBackend.html b/docs/WritingAnLLVMBackend.html index d909a1a3fb..077dea0ed6 100644 --- a/docs/WritingAnLLVMBackend.html +++ b/docs/WritingAnLLVMBackend.html @@ -1310,7 +1310,8 @@ implementation in <tt>SparcInstrInfo.cpp</tt>: a direct store to a stack slot, return the register number of the destination and the <tt>FrameIndex</tt> of the stack slot.</li> -<li><tt>copyRegToReg</tt> — Copy values between a pair of registers.</li> +<li><tt>copyPhysReg</tt> — Copy values between a pair of physical + registers.</li> <li><tt>storeRegToStackSlot</tt> — Store a register value to a stack slot.</li> diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 6a4573b4fd..6e69914320 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -357,7 +357,9 @@ public: virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, - bool KillSrc) const =0; + bool KillSrc) const { + assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!"); + } /// storeRegToStackSlot - Store the specified register of the given register /// class to the specified stack frame index. The store instruction is to be @@ -648,22 +650,6 @@ public: virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const; - virtual void copyPhysReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, DebugLoc DL, - unsigned DestReg, unsigned SrcReg, - bool KillSrc) const; - /// copyRegToReg - Legacy hook going away soon. Targets should implement - /// copyPhysReg instead. - virtual bool copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC, - DebugLoc DL) const { - assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!"); - return false; - } - }; } // End llvm namespace diff --git a/include/llvm/Target/TargetOpcodes.h b/include/llvm/Target/TargetOpcodes.h index e710c70219..cb772ecd77 100644 --- a/include/llvm/Target/TargetOpcodes.h +++ b/include/llvm/Target/TargetOpcodes.h @@ -62,8 +62,7 @@ namespace TargetOpcode { /// used between instruction selection and MachineInstr creation, before /// virtual registers have been created for all the instructions, and it's /// only needed in cases where the register classes implied by the - /// instructions are insufficient. The actual MachineInstrs to perform - /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. + /// instructions are insufficient. It is emitted as a COPY MachineInstr. COPY_TO_REGCLASS = 10, /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp index 56cb4b19b8..5b1d5a62ff 100644 --- a/lib/CodeGen/TargetInstrInfoImpl.cpp +++ b/lib/CodeGen/TargetInstrInfoImpl.cpp @@ -438,20 +438,3 @@ ScheduleHazardRecognizer *TargetInstrInfoImpl:: CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const { return (ScheduleHazardRecognizer *)new PostRAHazardRecognizer(II); } - -// Default implementation of copyPhysReg using copyRegToReg. -void TargetInstrInfoImpl::copyPhysReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - DebugLoc DL, - unsigned DestReg, unsigned SrcReg, - bool KillSrc) const { - assert(TargetRegisterInfo::isPhysicalRegister(DestReg)); - assert(TargetRegisterInfo::isPhysicalRegister(SrcReg)); - const TargetRegisterInfo *TRI = MBB.getParent()->getTarget().getRegisterInfo(); - const TargetRegisterClass *DRC = TRI->getPhysicalRegisterRegClass(DestReg); - const TargetRegisterClass *SRC = TRI->getPhysicalRegisterRegClass(SrcReg); - if (!copyRegToReg(MBB, MI, DestReg, SrcReg, DRC, SRC, DL)) - llvm_unreachable("Cannot emit physreg copy instruction"); - if (KillSrc) - llvm::prior(MI)->addRegisterKilled(SrcReg, TRI, true); -} diff --git a/test/CodeGen/Blackfin/cmp64.ll b/test/CodeGen/Blackfin/cmp64.ll index ef5bf45861..6c4f9c5bd7 100644 --- a/test/CodeGen/Blackfin/cmp64.ll +++ b/test/CodeGen/Blackfin/cmp64.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=bfin ; This test tries to use a JustCC register as a data operand for MOVEcc. It -; calls copyRegToReg(JustCC -> DP), failing because JustCC can only be copied to -; D. The proper solution would be to restrict the virtual register to D only. +; copies (JustCC -> DP), failing because JustCC can only be copied to D. +; The proper solution would be to restrict the virtual register to D only. define i32 @main() { entry: diff --git a/test/TableGen/TargetInstrInfo.td b/test/TableGen/TargetInstrInfo.td index 2871eb81df..146ef6fd76 100644 --- a/test/TableGen/TargetInstrInfo.td +++ b/test/TableGen/TargetInstrInfo.td @@ -83,8 +83,7 @@ class Inst<dag opnds, string asmstr, bits<8> opcode, // the pattern. // 6. Address expressions should become first-class entities. -// Simple copy instruction. isMoveInstr could easily be inferred from this, -// as could TargetRegisterInfo::copyRegToReg. +// Simple copy instruction. def MOV8rr : Inst<(ops R8:$dst, R8:$src), "mov $dst, $src", 0x88, MRMDestReg, [(set R8:$dst, R8:$src)]>; |