diff options
83 files changed, 423 insertions, 339 deletions
diff --git a/include/llvm/Object/ELF.h b/include/llvm/Object/ELF.h index 1c34cf1485..9e8b6fafd8 100644 --- a/include/llvm/Object/ELF.h +++ b/include/llvm/Object/ELF.h @@ -582,7 +582,6 @@ protected: private: typedef SmallVector<const Elf_Shdr *, 2> Sections_t; typedef DenseMap<unsigned, unsigned> IndexMap_t; - typedef DenseMap<const Elf_Shdr*, SmallVector<uint32_t, 1> > RelocMap_t; const Elf_Ehdr *Header; const Elf_Shdr *SectionHeaderTable; @@ -634,13 +633,9 @@ private: void LoadVersionNeeds(const Elf_Shdr *ec) const; void LoadVersionMap() const; - /// @brief Map sections to an array of relocation sections that reference - /// them sorted by section index. - RelocMap_t SectionRelocMap; - /// @brief Get the relocation section that contains \a Rel. const Elf_Shdr *getRelSection(DataRefImpl Rel) const { - return getSection(Rel.w.b); + return getSection(Rel.d.a); } public: @@ -712,6 +707,7 @@ protected: bool &Result) const; virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const; virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const; + virtual section_iterator getRelocatedSection(DataRefImpl Sec) const; virtual error_code getRelocationNext(DataRefImpl Rel, RelocationRef &Res) const; @@ -1458,13 +1454,9 @@ template<class ELFT> relocation_iterator ELFObjectFile<ELFT>::getSectionRelBegin(DataRefImpl Sec) const { DataRefImpl RelData; - const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p); - typename RelocMap_t::const_iterator ittr = SectionRelocMap.find(sec); - if (sec != 0 && ittr != SectionRelocMap.end()) { - RelData.w.a = getSection(ittr->second[0])->sh_info; - RelData.w.b = ittr->second[0]; - RelData.w.c = 0; - } + uintptr_t SHT = reinterpret_cast<uintptr_t>(SectionHeaderTable); + RelData.d.a = (Sec.p - SHT) / Header->e_shentsize; + RelData.d.b = 0; return relocation_iterator(RelocationRef(RelData, this)); } @@ -1472,44 +1464,41 @@ template<class ELFT> relocation_iterator ELFObjectFile<ELFT>::getSectionRelEnd(DataRefImpl Sec) const { DataRefImpl RelData; - const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p); - typename RelocMap_t::const_iterator ittr = SectionRelocMap.find(sec); - if (sec != 0 && ittr != SectionRelocMap.end()) { - // Get the index of the last relocation section for this section. - std::size_t relocsecindex = ittr->second[ittr->second.size() - 1]; - const Elf_Shdr *relocsec = getSection(relocsecindex); - RelData.w.a = relocsec->sh_info; - RelData.w.b = relocsecindex; - RelData.w.c = relocsec->sh_size / relocsec->sh_entsize; - } + uintptr_t SHT = reinterpret_cast<uintptr_t>(SectionHeaderTable); + const Elf_Shdr *S = reinterpret_cast<const Elf_Shdr *>(Sec.p); + RelData.d.a = (Sec.p - SHT) / Header->e_shentsize; + if (S->sh_type != ELF::SHT_RELA && S->sh_type != ELF::SHT_REL) + RelData.d.b = 0; + else + RelData.d.b = S->sh_size / S->sh_entsize; + return relocation_iterator(RelocationRef(RelData, this)); } +template <class ELFT> +section_iterator +ELFObjectFile<ELFT>::getRelocatedSection(DataRefImpl Sec) const { + if (Header->e_type != ELF::ET_REL) + return end_sections(); + + const Elf_Shdr *S = reinterpret_cast<const Elf_Shdr *>(Sec.p); + unsigned sh_type = S->sh_type; + if (sh_type != ELF::SHT_RELA && sh_type != ELF::SHT_REL) + return end_sections(); + + unsigned SecIndex = S->sh_info; + assert(SecIndex != 0); + const Elf_Shdr *R = getSection(S->sh_info); + DataRefImpl D; + D.p = reinterpret_cast<uintptr_t>(R); + return section_iterator(SectionRef(D, this)); +} + // Relocations template<class ELFT> error_code ELFObjectFile<ELFT>::getRelocationNext(DataRefImpl Rel, RelocationRef &Result) const { - ++Rel.w.c; - const Elf_Shdr *relocsec = getSection(Rel.w.b); - if (Rel.w.c >= (relocsec->sh_size / relocsec->sh_entsize)) { - // We have reached the end of the relocations for this section. See if there - // is another relocation section. - typename RelocMap_t::mapped_type relocseclist = - SectionRelocMap.lookup(getSection(Rel.w.a)); - - // Do a binary search for the current reloc section index (which must be - // present). Then get the next one. - typename RelocMap_t::mapped_type::const_iterator loc = - std::lower_bound(relocseclist.begin(), relocseclist.end(), Rel.w.b); - ++loc; - - // If there is no next one, don't do anything. The ++Rel.w.c above sets Rel - // to the end iterator. - if (loc != relocseclist.end()) { - Rel.w.b = *loc; - Rel.w.a = 0; - } - } + ++Rel.d.b; Result = RelocationRef(Rel, this); return object_error::success; } @@ -1518,7 +1507,7 @@ template<class ELFT> error_code ELFObjectFile<ELFT>::getRelocationSymbol(DataRefImpl Rel, SymbolRef &Result) const { uint32_t symbolIdx; - const Elf_Shdr *sec = getSection(Rel.w.b); + const Elf_Shdr *sec = getRelSection(Rel); switch (sec->sh_type) { default : report_fatal_error("Invalid section type in Rel!"); @@ -1561,7 +1550,7 @@ error_code ELFObjectFile<ELFT>::getRelocationOffset(DataRefImpl Rel, template<class ELFT> uint64_t ELFObjectFile<ELFT>::getROffset(DataRefImpl Rel) const { - const Elf_Shdr *sec = getSection(Rel.w.b); + const Elf_Shdr *sec = getRelSection(Rel); switch (sec->sh_type) { default: report_fatal_error("Invalid section type in Rel!"); @@ -1575,7 +1564,7 @@ uint64_t ELFObjectFile<ELFT>::getROffset(DataRefImpl Rel) const { template<class ELFT> error_code ELFObjectFile<ELFT>::getRelocationType(DataRefImpl Rel, uint64_t &Result) const { - const Elf_Shdr *sec = getSection(Rel.w.b); + const Elf_Shdr *sec = getRelSection(Rel); switch (sec->sh_type) { default : report_fatal_error("Invalid section type in Rel!"); @@ -2192,7 +2181,7 @@ StringRef ELFObjectFile<ELFT>::getRelocationTypeName(uint32_t Type) const { template<class ELFT> error_code ELFObjectFile<ELFT>::getRelocationTypeName( DataRefImpl Rel, SmallVectorImpl<char> &Result) const { - const Elf_Shdr *sec = getSection(Rel.w.b); + const Elf_Shdr *sec = getRelSection(Rel); uint32_t type; switch (sec->sh_type) { default : @@ -2234,7 +2223,7 @@ error_code ELFObjectFile<ELFT>::getRelocationTypeName( template<class ELFT> error_code ELFObjectFile<ELFT>::getRelocationAddend( DataRefImpl Rel, int64_t &Result) const { - const Elf_Shdr *sec = getSection(Rel.w.b); + const Elf_Shdr *sec = getRelSection(Rel); switch (sec->sh_type) { default : report_fatal_error("Invalid section type in Rel!"); @@ -2252,7 +2241,7 @@ error_code ELFObjectFile<ELFT>::getRelocationAddend( template<class ELFT> error_code ELFObjectFile<ELFT>::getRelocationValueString( DataRefImpl Rel, SmallVectorImpl<char> &Result) const { - const Elf_Shdr *sec = getSection(Rel.w.b); + const Elf_Shdr *sec = getRelSection(Rel); uint8_t type; StringRef res; int64_t addend = 0; @@ -2402,10 +2391,8 @@ ELFObjectFile<ELFT>::ELFObjectFile(MemoryBuffer *Object, error_code &ec) break; } case ELF::SHT_REL: - case ELF::SHT_RELA: { - SectionRelocMap[getSection(sh->sh_info)].push_back(i); + case ELF::SHT_RELA: break; - } case ELF::SHT_DYNAMIC: { if (dot_dynamic_sec != NULL) // FIXME: Proper error handling. @@ -2438,12 +2425,6 @@ ELFObjectFile<ELFT>::ELFObjectFile(MemoryBuffer *Object, error_code &ec) ++sh; } - // Sort section relocation lists by index. - for (typename RelocMap_t::iterator i = SectionRelocMap.begin(), - e = SectionRelocMap.end(); i != e; ++i) { - std::sort(i->second.begin(), i->second.end()); - } - // Get string table sections. dot_shstrtab_sec = getSection(getStringTableIndex()); if (dot_shstrtab_sec) { @@ -2795,13 +2776,13 @@ ELFObjectFile<ELFT>::getSymbol(DataRefImpl Symb) const { template<class ELFT> const typename ELFObjectFile<ELFT>::Elf_Rel * ELFObjectFile<ELFT>::getRel(DataRefImpl Rel) const { - return getEntry<Elf_Rel>(Rel.w.b, Rel.w.c); + return getEntry<Elf_Rel>(Rel.d.a, Rel.d.b); } template<class ELFT> const typename ELFObjectFile<ELFT>::Elf_Rela * ELFObjectFile<ELFT>::getRela(DataRefImpl Rela) const { - return getEntry<Elf_Rela>(Rela.w.b, Rela.w.c); + return getEntry<Elf_Rela>(Rela.d.a, Rela.d.b); } template<class ELFT> diff --git a/include/llvm/Object/ObjectFile.h b/include/llvm/Object/ObjectFile.h index c73a568c1c..ba1bb6945b 100644 --- a/include/llvm/Object/ObjectFile.h +++ b/include/llvm/Object/ObjectFile.h @@ -28,12 +28,8 @@ namespace object { class ObjectFile; union DataRefImpl { - struct { - // ELF needs this for relocations. This entire union should probably be a - // char[max(8, sizeof(uintptr_t))] and require the impl to cast. - uint16_t a, b; - uint32_t c; - } w; + // This entire union should probably be a + // char[max(8, sizeof(uintptr_t))] and require the impl to cast. struct { uint32_t a, b; } d; @@ -133,6 +129,8 @@ typedef content_iterator<RelocationRef> relocation_iterator; /// SectionRef - This is a value type class that represents a single section in /// the list of sections in the object file. +class SectionRef; +typedef content_iterator<SectionRef> section_iterator; class SectionRef { friend class SymbolRef; DataRefImpl SectionPimpl; @@ -169,10 +167,10 @@ public: relocation_iterator begin_relocations() const; relocation_iterator end_relocations() const; + section_iterator getRelocatedSection() const; DataRefImpl getRawDataRefImpl() const; }; -typedef content_iterator<SectionRef> section_iterator; /// SymbolRef - This is a value type class that represents a single symbol in /// the list of symbols in the object file. @@ -326,7 +324,7 @@ protected: bool &Result) const = 0; virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const = 0; virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const = 0; - + virtual section_iterator getRelocatedSection(DataRefImpl Sec) const; // Same as above for RelocationRef. friend class RelocationRef; @@ -538,6 +536,10 @@ inline relocation_iterator SectionRef::end_relocations() const { return OwningObject->getSectionRelEnd(SectionPimpl); } +inline section_iterator SectionRef::getRelocatedSection() const { + return OwningObject->getRelocatedSection(SectionPimpl); +} + inline DataRefImpl SectionRef::getRawDataRefImpl() const { return SectionPimpl; } diff --git a/lib/DebugInfo/DWARFContext.cpp b/lib/DebugInfo/DWARFContext.cpp index 9f521330c3..7e4132f059 100644 --- a/lib/DebugInfo/DWARFContext.cpp +++ b/lib/DebugInfo/DWARFContext.cpp @@ -19,6 +19,7 @@ #include <algorithm> using namespace llvm; using namespace dwarf; +using namespace object; typedef DWARFDebugLine::LineTable DWARFLineTable; @@ -554,17 +555,26 @@ DWARFContextInMemory::DWARFContextInMemory(object::ObjectFile *Obj) : .Case("debug_addr", &AddrSection) // Any more debug info sections go here. .Default(0); - if (!Section) - continue; - *Section = data; - if (name == "debug_ranges") { - // FIXME: Use the other dwo range section when we emit it. - RangeDWOSection = data; + if (Section) { + *Section = data; + if (name == "debug_ranges") { + // FIXME: Use the other dwo range section when we emit it. + RangeDWOSection = data; + } } + section_iterator RelocatedSection = i->getRelocatedSection(); + if (RelocatedSection == Obj->end_sections()) + continue; + + StringRef RelSecName; + RelocatedSection->getName(RelSecName); + RelSecName = RelSecName.substr( + RelSecName.find_first_not_of("._")); // Skip . and _ prefixes. + // TODO: Add support for relocations in other sections as needed. // Record relocations for the debug_info and debug_line sections. - RelocAddrMap *Map = StringSwitch<RelocAddrMap*>(name) + RelocAddrMap *Map = StringSwitch<RelocAddrMap*>(RelSecName) .Case("debug_info", &InfoRelocMap) .Case("debug_info.dwo", &InfoDWORelocMap) .Case("debug_line", &LineRelocMap) @@ -574,7 +584,7 @@ DWARFContextInMemory::DWARFContextInMemory(object::ObjectFile *Obj) : if (i->begin_relocations() != i->end_relocations()) { uint64_t SectionSize; - i->getSize(SectionSize); + RelocatedSection->getSize(SectionSize); for (object::relocation_iterator reloc_i = i->begin_relocations(), reloc_e = i->end_relocations(); reloc_i != reloc_e; reloc_i.increment(ec)) { diff --git a/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp b/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp index 844f1c2931..cee18c69ad 100644 --- a/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp +++ b/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp @@ -19,6 +19,7 @@ #include "RuntimeDyldMachO.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Path.h" +#include "llvm/Object/ELF.h" using namespace llvm; using namespace llvm::object; @@ -146,6 +147,7 @@ ObjectImage *RuntimeDyldImpl::loadObject(ObjectBuffer *InputBuffer) { bool isFirstRelocation = true; unsigned SectionID = 0; StubMap Stubs; + section_iterator RelocatedSection = si->getRelocatedSection(); for (relocation_iterator i = si->begin_relocations(), e = si->end_relocations(); i != e; i.increment(err)) { @@ -153,7 +155,8 @@ ObjectImage *RuntimeDyldImpl::loadObject(ObjectBuffer *InputBuffer) { // If it's the first relocation in this section, find its SectionID if (isFirstRelocation) { - SectionID = findOrEmitSection(*obj, *si, true, LocalSections); + SectionID = + findOrEmitSection(*obj, *RelocatedSection, true, LocalSections); DEBUG(dbgs() << "\tSectionID: " << SectionID << "\n"); isFirstRelocation = false; } @@ -214,11 +217,25 @@ unsigned RuntimeDyldImpl::emitSection(ObjectImage &Obj, unsigned StubBufSize = 0, StubSize = getMaxStubSize(); error_code err; + const ObjectFile *ObjFile = Obj.getObjectFile(); + // FIXME: this is an inefficient way to handle this. We should computed the + // necessary section allocation size in loadObject by walking all the sections + // once. if (StubSize > 0) { - for (relocation_iterator i = Section.begin_relocations(), - e = Section.end_relocations(); i != e; i.increment(err), Check(err)) - StubBufSize += StubSize; + for (section_iterator SI = ObjFile->begin_sections(), + SE = ObjFile->end_sections(); + SI != SE; SI.increment(err), Check(err)) { + section_iterator RelSecI = SI->getRelocatedSection(); + if (!(RelSecI == Section)) + continue; + + for (relocation_iterator I = SI->begin_relocations(), + E = SI->end_relocations(); I != E; I.increment(err), Check(err)) { + StubBufSize += StubSize; + } + } } + StringRef data; uint64_t Alignment64; Check(Section.getContents(data)); diff --git a/lib/MC/MCObjectSymbolizer.cpp b/lib/MC/MCObjectSymbolizer.cpp index e1d504ec8e..1803498991 100644 --- a/lib/MC/MCObjectSymbolizer.cpp +++ b/lib/MC/MCObjectSymbolizer.cpp @@ -71,10 +71,14 @@ MCObjectSymbolizer::MCObjectSymbolizer(MCContext &Ctx, SI != SE; SI.increment(ec)) { if (ec) break; - uint64_t StartAddr; SI->getAddress(StartAddr); - uint64_t Size; SI->getSize(Size); - StringRef SecName; SI->getName(SecName); - bool RequiredForExec; SI->isRequiredForExecution(RequiredForExec); + + section_iterator RelSecI = SI->getRelocatedSection(); + if (RelSecI == Obj->end_sections()) + continue; + + uint64_t StartAddr; RelSecI->getAddress(StartAddr); + uint64_t Size; RelSecI->getSize(Size); + bool RequiredForExec; RelSecI->isRequiredForExecution(RequiredForExec); if (RequiredForExec == false || Size == 0) continue; AddrToSection.insert(StartAddr, StartAddr + Size - 1, diff --git a/lib/Object/ObjectFile.cpp b/lib/Object/ObjectFile.cpp index 77fd995cf0..5b3165db94 100644 --- a/lib/Object/ObjectFile.cpp +++ b/lib/Object/ObjectFile.cpp @@ -33,6 +33,10 @@ error_code ObjectFile::getSymbolAlignment(DataRefImpl DRI, return object_error::success; } +section_iterator ObjectFile::getRelocatedSection(DataRefImpl Sec) const { + return section_iterator(SectionRef(Sec, this)); +} + ObjectFile *ObjectFile::createObjectFile(MemoryBuffer *Object) { if (!Object || Object->getBufferSize() < 64) return 0; diff --git a/test/CodeGen/AArch64/adrp-relocation.ll b/test/CodeGen/AArch64/adrp-relocation.ll index cf411166a3..1e12d69b76 100644 --- a/test/CodeGen/AArch64/adrp-relocation.ll +++ b/test/CodeGen/AArch64/adrp-relocation.ll @@ -20,7 +20,7 @@ entry: ; object file's .text section gets relocated in memory. ; CHECK: Relocations [ -; CHECK-NEXT: Section (1) .text { +; CHECK-NEXT: Section (2) .rela.text { ; CHECK-NEXT: 0x10 R_AARCH64_ADR_PREL_PG_HI21 testfn 0x0 ; CHECK-NEXT: 0x14 R_AARCH64_ADD_ABS_LO12_NC testfn 0x0 ; CHECK-NEXT: } diff --git a/test/CodeGen/AArch64/basic-pic.ll b/test/CodeGen/AArch64/basic-pic.ll index da94041c95..5343cc793e 100644 --- a/test/CodeGen/AArch64/basic-pic.ll +++ b/test/CodeGen/AArch64/basic-pic.ll @@ -3,7 +3,7 @@ @var = global i32 0 -; CHECK-ELF: RELOCATION RECORDS FOR [.text] +; CHECK-ELF: RELOCATION RECORDS FOR [.rela.text] define i32 @get_globalvar() { ; CHECK: get_globalvar: diff --git a/test/CodeGen/AArch64/elf-extern.ll b/test/CodeGen/AArch64/elf-extern.ll index 8bf1b2ff4f..e09aa127ca 100644 --- a/test/CodeGen/AArch64/elf-extern.ll +++ b/test/CodeGen/AArch64/elf-extern.ll @@ -11,7 +11,7 @@ define i32 @check_extern() { } ; CHECK: Relocations [ -; CHECK: Section (1) .text { +; CHECK: Section (2) .rela.text { ; CHECK: 0x{{[0-9,A-F]+}} R_AARCH64_CALL26 memcpy ; CHECK: } ; CHECK: ] diff --git a/test/CodeGen/AArch64/jump-table.ll b/test/CodeGen/AArch64/jump-table.ll index 3c7f5f9ec1..0f1e760a36 100644 --- a/test/CodeGen/AArch64/jump-table.ll +++ b/test/CodeGen/AArch64/jump-table.ll @@ -54,13 +54,13 @@ lbl4: ; First make sure we get a page/lo12 pair in .text to pick up the jump-table ; CHECK-ELF: Relocations [ -; CHECK-ELF: Section ({{[0-9]+}}) .text { +; CHECK-ELF: Section ({{[0-9]+}}) .rela.text { ; CHECK-ELF-NEXT: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 .rodata ; CHECK-ELF-NEXT: 0x{{[0-9,A-F]+}} R_AARCH64_ADD_ABS_LO12_NC .rodata ; CHECK-ELF: } ; Also check the targets in .rodata are relocated -; CHECK-ELF: Section ({{[0-9]+}}) .rodata { +; CHECK-ELF: Section ({{[0-9]+}}) .rela.rodata { ; CHECK-ELF-NEXT: 0x{{[0-9,A-F]+}} R_AARCH64_ABS64 .text ; CHECK-ELF: } ; CHECK-ELF: ] diff --git a/test/CodeGen/ARM/2010-11-30-reloc-movt.ll b/test/CodeGen/ARM/2010-11-30-reloc-movt.ll index 9eecd045bf..6bea7b88e8 100644 --- a/test/CodeGen/ARM/2010-11-30-reloc-movt.ll +++ b/test/CodeGen/ARM/2010-11-30-reloc-movt.ll @@ -11,15 +11,15 @@ entry: ret i32 %0 ; OBJ: Section { ; OBJ: Name: .text +; OBJ: SectionData ( +; OBJ-NEXT: 0000: 00482DE9 000000E3 000040E3 FEFFFFEB +; OBJ-NEXT: 0010: 0088BDE8 +; OBJ-NEXT: ) ; OBJ: Relocations [ ; OBJ-NEXT: 0x4 R_ARM_MOVW_ABS_NC a ; OBJ-NEXT: 0x8 R_ARM_MOVT_ABS ; OBJ-NEXT: 0xC R_ARM_CALL foo ; OBJ-NEXT: ] -; OBJ-NEXT: SectionData ( -; OBJ-NEXT: 0000: 00482DE9 000000E3 000040E3 FEFFFFEB -; OBJ-NEXT: 0010: 0088BDE8 -; OBJ-NEXT: ) } diff --git a/test/CodeGen/ARM/ehabi-mc-compact-pr0.ll b/test/CodeGen/ARM/ehabi-mc-compact-pr0.ll index 11f3e6db0f..637a989240 100644 --- a/test/CodeGen/ARM/ehabi-mc-compact-pr0.ll +++ b/test/CodeGen/ARM/ehabi-mc-compact-pr0.ll @@ -44,6 +44,6 @@ declare void @_Z15throw_exceptionv() ; CHECK-FP-ELIM-NEXT: 0000 00000000 b0808480 ; CHECK-FP-ELIM-NOT: section .ARM.extab -; CHECK-RELOC: RELOCATION RECORDS FOR [.ARM.exidx] +; CHECK-RELOC: RELOCATION RECORDS FOR [.rel.ARM.exidx] ; CHECK-RELOC-NEXT: 0 R_ARM_PREL31 .text ; CHECK-RELOC-NEXT: 0 R_ARM_NONE __aeabi_unwind_cpp_pr0 diff --git a/test/CodeGen/ARM/ehabi-mc-compact-pr1.ll b/test/CodeGen/ARM/ehabi-mc-compact-pr1.ll index 79dba084c0..5a54889d6a 100644 --- a/test/CodeGen/ARM/ehabi-mc-compact-pr1.ll +++ b/test/CodeGen/ARM/ehabi-mc-compact-pr1.ll @@ -53,10 +53,10 @@ declare void @_Z15throw_exceptioni(i32) ; CHECK-FP-ELIM-NEXT: 0000 00000000 b0838480 ; CHECK-FP-ELIM-NOT: section .ARM.extab -; CHECK-RELOC: RELOCATION RECORDS FOR [.ARM.exidx] +; CHECK-RELOC: RELOCATION RECORDS FOR [.rel.ARM.exidx] ; CHECK-RELOC-NEXT: 0 R_ARM_PREL31 .text ; CHECK-RELOC-NEXT: 0 R_ARM_NONE __aeabi_unwind_cpp_pr1 -; CHECK-FP-ELIM-RELOC: RELOCATION RECORDS FOR [.ARM.exidx] +; CHECK-FP-ELIM-RELOC: RELOCATION RECORDS FOR [.rel.ARM.exidx] ; CHECK-FP-ELIM-RELOC-NEXT: 0 R_ARM_PREL31 .text ; CHECK-FP-ELIM-RELOC-NEXT: 0 R_ARM_NONE __aeabi_unwind_cpp_pr0 diff --git a/test/CodeGen/PowerPC/mcm-obj-2.ll b/test/CodeGen/PowerPC/mcm-obj-2.ll index bc60b3baf2..a6e9855451 100644 --- a/test/CodeGen/PowerPC/mcm-obj-2.ll +++ b/test/CodeGen/PowerPC/mcm-obj-2.ll @@ -20,7 +20,7 @@ entry: ; accessing function-scoped variable si. ; ; CHECK: Relocations [ -; CHECK: Section (1) .text { +; CHECK: Section (2) .rela.text { ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]] ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]] ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]] diff --git a/test/CodeGen/PowerPC/mcm-obj.ll b/test/CodeGen/PowerPC/mcm-obj.ll index 720c5fb6dd..4550c39f15 100644 --- a/test/CodeGen/PowerPC/mcm-obj.ll +++ b/test/CodeGen/PowerPC/mcm-obj.ll @@ -22,12 +22,12 @@ entry: ; accessing external variable ei. ; ; MEDIUM: Relocations [ -; MEDIUM: Section (1) .text { +; MEDIUM: Section (2) .rela.text { ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]] ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]] ; ; LARGE: Relocations [ -; LARGE: Section (1) .text { +; LARGE: Section (2) .rela.text { ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]] ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]] diff --git a/test/CodeGen/PowerPC/tls-gd-obj.ll b/test/CodeGen/PowerPC/tls-gd-obj.ll index ffc0db0d14..26cb6f28ef 100644 --- a/test/CodeGen/PowerPC/tls-gd-obj.ll +++ b/test/CodeGen/PowerPC/tls-gd-obj.ll @@ -22,7 +22,7 @@ entry: ; for the call to __tls_get_addr. ; ; CHECK: Relocations [ -; CHECK: Section (1) .text { +; CHECK: Section (2) .rela.text { ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_HA a ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_LO a ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLSGD a diff --git a/test/CodeGen/PowerPC/tls-ie-obj.ll b/test/CodeGen/PowerPC/tls-ie-obj.ll index 0f7a352952..f24a94bdb0 100644 --- a/test/CodeGen/PowerPC/tls-ie-obj.ll +++ b/test/CodeGen/PowerPC/tls-ie-obj.ll @@ -21,7 +21,7 @@ entry: ; accessing external variable a. ; ; CHECK: Relocations [ -; CHECK: Section (1) .text { +; CHECK: Section (2) .rela.text { ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA a ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS a ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLS a diff --git a/test/CodeGen/PowerPC/tls-ld-obj.ll b/test/CodeGen/PowerPC/tls-ld-obj.ll index 29ee876845..4a7d7b3f91 100644 --- a/test/CodeGen/PowerPC/tls-ld-obj.ll +++ b/test/CodeGen/PowerPC/tls-ld-obj.ll @@ -23,7 +23,7 @@ entry: ; __tls_get_addr. ; ; CHECK: Relocations [ -; CHECK: Section (1) .text { +; CHECK: Section (2) .rela.text { ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_HA a ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_LO a ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLSLD a diff --git a/test/MC/AArch64/elf-globaladdress.ll b/test/MC/AArch64/elf-globaladdress.ll index 942920be4d..bc43113fee 100644 --- a/test/MC/AArch64/elf-globaladdress.ll +++ b/test/MC/AArch64/elf-globaladdress.ll @@ -40,7 +40,7 @@ define void @address() { ; OBJ: } ; OBJ: Relocations [ -; OBJ: Section (1) .text { +; OBJ: Section (2) .rela.text { ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var8 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST8_ABS_LO12_NC var8 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var16 diff --git a/test/MC/AArch64/elf-reloc-addsubimm.s b/test/MC/AArch64/elf-reloc-addsubimm.s index 0321dda332..e37991bfba 100644 --- a/test/MC/AArch64/elf-reloc-addsubimm.s +++ b/test/MC/AArch64/elf-reloc-addsubimm.s @@ -4,7 +4,7 @@ add x2, x3, #:lo12:some_label // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_ADD_ABS_LO12_NC some_label 0x0 // OBJ-NEXT: } // OBJ-NEXT: ] diff --git a/test/MC/AArch64/elf-reloc-condbr.s b/test/MC/AArch64/elf-reloc-condbr.s index 684e75a33c..b70dfa70fb 100644 --- a/test/MC/AArch64/elf-reloc-condbr.s +++ b/test/MC/AArch64/elf-reloc-condbr.s @@ -4,7 +4,7 @@ b.eq somewhere // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_CONDBR19 somewhere 0x0 // OBJ-NEXT: } // OBJ-NEXT: ] diff --git a/test/MC/AArch64/elf-reloc-ldrlit.s b/test/MC/AArch64/elf-reloc-ldrlit.s index de43c4feac..d4c3a4eb50 100644 --- a/test/MC/AArch64/elf-reloc-ldrlit.s +++ b/test/MC/AArch64/elf-reloc-ldrlit.s @@ -7,7 +7,7 @@ prfm pldl3keep, some_label // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_LD_PREL_LO19 some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_LD_PREL_LO19 some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_LD_PREL_LO19 some_label 0x0 diff --git a/test/MC/AArch64/elf-reloc-ldstunsimm.s b/test/MC/AArch64/elf-reloc-ldstunsimm.s index e1f841bd20..64bf63aa97 100644 --- a/test/MC/AArch64/elf-reloc-ldstunsimm.s +++ b/test/MC/AArch64/elf-reloc-ldstunsimm.s @@ -8,7 +8,7 @@ str q0, [sp, #:lo12:some_label] // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_LDST8_ABS_LO12_NC some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_LDST16_ABS_LO12_NC some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_LDST32_ABS_LO12_NC some_label 0x0 diff --git a/test/MC/AArch64/elf-reloc-movw.s b/test/MC/AArch64/elf-reloc-movw.s index 8a7e532cdd..333159562c 100644 --- a/test/MC/AArch64/elf-reloc-movw.s +++ b/test/MC/AArch64/elf-reloc-movw.s @@ -23,7 +23,7 @@ movn x19, #:abs_g2_s:some_label // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_MOVW_UABS_G0 some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_MOVW_UABS_G0_NC some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_MOVW_UABS_G1 some_label 0x0 diff --git a/test/MC/AArch64/elf-reloc-pcreladdressing.s b/test/MC/AArch64/elf-reloc-pcreladdressing.s index b5f072712f..093891d931 100644 --- a/test/MC/AArch64/elf-reloc-pcreladdressing.s +++ b/test/MC/AArch64/elf-reloc-pcreladdressing.s @@ -8,7 +8,7 @@ ldr x0, [x5, #:got_lo12:some_label] // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_ADR_PREL_LO21 some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_ADR_PREL_PG_HI21 some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_ADR_GOT_PAGE some_label 0x0 diff --git a/test/MC/AArch64/elf-reloc-tstb.s b/test/MC/AArch64/elf-reloc-tstb.s index 037e89632e..25c98163b5 100644 --- a/test/MC/AArch64/elf-reloc-tstb.s +++ b/test/MC/AArch64/elf-reloc-tstb.s @@ -5,7 +5,7 @@ tbnz w3, #15, somewhere // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_TSTBR14 somewhere 0x0 // OBJ-NEXT: 0x4 R_AARCH64_TSTBR14 somewhere 0x0 // OBJ-NEXT: } diff --git a/test/MC/AArch64/elf-reloc-uncondbrimm.s b/test/MC/AArch64/elf-reloc-uncondbrimm.s index bead07c12d..9ac66bd876 100644 --- a/test/MC/AArch64/elf-reloc-uncondbrimm.s +++ b/test/MC/AArch64/elf-reloc-uncondbrimm.s @@ -5,7 +5,7 @@ bl somewhere // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_JUMP26 somewhere 0x0 // OBJ-NEXT: 0x4 R_AARCH64_CALL26 somewhere 0x0 // OBJ-NEXT: } diff --git a/test/MC/AArch64/tls-relocs.s b/test/MC/AArch64/tls-relocs.s index d0e336ecaf..5cbd794ac9 100644 --- a/test/MC/AArch64/tls-relocs.s +++ b/test/MC/AArch64/tls-relocs.s @@ -17,7 +17,7 @@ // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 // CHECK-ELF: Relocations [ -// CHECK-ELF-NEXT: Section (1) .text { +// CHECK-ELF-NEXT: Section (2) .rela.text { // CHECK-ELF-NEXT: 0x0 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM:[^ ]+]] // CHECK-ELF-NEXT: 0x4 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] // CHECK-ELF-NEXT: 0x8 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] diff --git a/test/MC/ARM/eh-compact-pr0.s b/test/MC/ARM/eh-compact-pr0.s index 6b866d5538..1d825bf3dd 100644 --- a/test/MC/ARM/eh-compact-pr0.s +++ b/test/MC/ARM/eh-compact-pr0.s @@ -50,15 +50,6 @@ func2: @ CHECK: Section { @ CHECK: Name: .ARM.exidx.TEST1 @------------------------------------------------------------------------------- -@ The first word should be relocated to .TEST1 section. Besides, there is -@ another relocation entry for __aeabi_unwind_cpp_pr0, so that the linker -@ will keep __aeabi_unwind_cpp_pr0. -@------------------------------------------------------------------------------- -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 -@ CHECK: ] -@------------------------------------------------------------------------------- @ 0x80 = Compact model 0, personality routine: __aeabi_unwind_cpp_pr0 @ 0x9B = $sp can be found in $r11 @ 0x8480 = pop {r11, r14} @@ -67,6 +58,15 @@ func2: @ CHECK: 0000: 00000000 80849B80 |........| @ CHECK: ) @ CHECK: } +@------------------------------------------------------------------------------- +@ The first word should be relocated to .TEST1 section. Besides, there is +@ another relocation entry for __aeabi_unwind_cpp_pr0, so that the linker +@ will keep __aeabi_unwind_cpp_pr0. +@------------------------------------------------------------------------------- +@ CHECK: Relocations [ +@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0 +@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ CHECK: ] @------------------------------------------------------------------------------- @@ -84,15 +84,6 @@ func2: @ CHECK: Section { @ CHECK: Name: .ARM.exidx.TEST2 @------------------------------------------------------------------------------- -@ The first word should be relocated to .TEST2 section. Besides, there is -@ another relocation entry for __aeabi_unwind_cpp_pr0, so that the linker -@ will keep __aeabi_unwind_cpp_pr0. -@------------------------------------------------------------------------------- -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST2 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 -@ CHECK: ] -@------------------------------------------------------------------------------- @ 0x80 = Compact model 0, personality routine: __aeabi_unwind_cpp_pr0 @ 0x8480 = pop {r11, r14} @ 0xB0 = finish @@ -102,3 +93,12 @@ func2: @ CHECK: ) @ CHECK: } @ CHECK: ] +@------------------------------------------------------------------------------- +@ The first word should be relocated to .TEST2 section. Besides, there is +@ another relocation entry for __aeabi_unwind_cpp_pr0, so that the linker +@ will keep __aeabi_unwind_cpp_pr0. +@------------------------------------------------------------------------------- +@ CHECK: Relocations [ +@ CHECK: 0x0 R_ARM_PREL31 .TEST2 0x0 +@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ CHECK: ] diff --git a/test/MC/ARM/eh-compact-pr1.s b/test/MC/ARM/eh-compact-pr1.s index 0fac3e2100..41971d0c44 100644 --- a/test/MC/ARM/eh-compact-pr1.s +++ b/test/MC/ARM/eh-compact-pr1.s @@ -56,6 +56,11 @@ func1: @------------------------------------------------------------------------------- @ CHECK: Section { @ CHECK: Name: .ARM.exidx.TEST1 +@ CHECK: SectionData ( +@ CHECK: 0000: 00000000 00000000 |........| +@ CHECK: ) +@ CHECK: } +@ CHECK: ] @------------------------------------------------------------------------------- @ The first word should be relocated to .TEST1 section, and the second word @ should be relocated to .ARM.extab.TEST1 section. Besides, there is @@ -67,8 +72,3 @@ func1: @ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0 @ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 @ CHECK: ] -@ CHECK: SectionData ( -@ CHECK: 0000: 00000000 00000000 |........| -@ CHECK: ) -@ CHECK: } -@ CHECK: ] diff --git a/test/MC/ARM/eh-directive-cantunwind.s b/test/MC/ARM/eh-directive-cantunwind.s index 0545f6d3c8..499c2c44df 100644 --- a/test/MC/ARM/eh-directive-cantunwind.s +++ b/test/MC/ARM/eh-directive-cantunwind.s @@ -37,9 +37,6 @@ func1: @------------------------------------------------------------------------------- @ CHECK: Section { @ CHECK: Name: .ARM.exidx -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .text 0x0 -@ CHECK: ] @------------------------------------------------------------------------------- @ The first word should be the offset to .text. @ The second word should be EXIDX_CANTUNWIND (01000000). @@ -49,3 +46,6 @@ func1: @ CHECK: ) @ CHECK: } @ CHECK: ] +@ CHECK: Relocations [ +@ CHECK: 0x0 R_ARM_PREL31 .text 0x0 +@ CHECK: ] diff --git a/test/MC/ARM/eh-directive-handlerdata.s b/test/MC/ARM/eh-directive-handlerdata.s index 45f22ddb63..793d357bac 100644 --- a/test/MC/ARM/eh-directive-handlerdata.s +++ b/test/MC/ARM/eh-directive-handlerdata.s @@ -35,6 +35,10 @@ func1: @ CHECK:Section { @ CHECK: Name: .ARM.exidx.TEST1 +@ CHECK: SectionData ( +@ CHECK: 0000: 00000000 00000000 |........| +@ CHECK: ) +@ CHECK:} @------------------------------------------------------------------------------- @ We should see a relocation entry to __aeabi_unwind_cpp_pr0, so that the @ linker can keep __aeabi_unwind_cpp_pr0. @@ -44,11 +48,6 @@ func1: @ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 @ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 @ CHECK: ] -@ CHECK: SectionData ( -@ CHECK: 0000: 00000000 00000000 |........| -@ CHECK: ) -@ CHECK:} - @@ -93,6 +92,10 @@ func2: @ CHECK:Section { @ CHECK: Name: .ARM.exidx.TEST2 +@ CHECK: SectionData ( +@ CHECK: 0000: 00000000 00000000 |........| +@ CHECK: ) +@ CHECK:} @------------------------------------------------------------------------------- @ We should see a relocation entry to __aeabi_unwind_cpp_pr0, so that the @ linker can keep __aeabi_unwind_cpp_pr0. @@ -102,7 +105,3 @@ func2: @ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0 @ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0 @ CHECK: ] -@ CHECK: SectionData ( -@ CHECK: 0000: 00000000 00000000 |........| -@ CHECK: ) -@ CHECK:} diff --git a/test/MC/ARM/eh-directive-personality.s b/test/MC/ARM/eh-directive-personality.s index 2267108b28..f493722957 100644 --- a/test/MC/ARM/eh-directive-personality.s +++ b/test/MC/ARM/eh-directive-personality.s @@ -28,24 +28,23 @@ func1: @ CHECK: } @ CHECK: Section { @ CHECK: Name: .ARM.extab.TEST1 -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 -@ CHECK: ] @ CHECK: SectionData ( @ CHECK: 0000: 00000000 B0B0B000 |........| @ CHECK: ) @ CHECK: } -@ CHECK: Section { -@ CHECK: Name: .ARM.exidx.TEST1 @ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 +@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 @ CHECK: ] +@ CHECK: Section { +@ CHECK: Name: .ARM.exidx.TEST1 @ CHECK: SectionData ( @ CHECK: 0000: 00000000 00000000 |........| @ CHECK: ) @ CHECK: } - +@ CHECK: Relocations [ +@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0 +@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 +@ CHECK: ] @------------------------------------------------------------------------------- @@ -71,20 +70,20 @@ func2: @ CHECK: } @ CHECK: Section { @ CHECK: Name: .ARM.extab.TEST2 -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 -@ CHECK: ] @ CHECK: SectionData ( @ CHECK: 0000: 00000000 B0B0B000 |........| @ CHECK: ) @ CHECK: } -@ CHECK: Section { -@ CHECK: Name: .ARM.exidx.TEST2 @ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST2 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0 +@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 @ CHECK: ] +@ CHECK: Section { +@ CHECK: Name: .ARM.exidx.TEST2 @ CHECK: SectionData ( @ CHECK: 0000: 00000000 00000000 |........| @ CHECK: ) @ CHECK: } +@ CHECK: Relocations [ +@ CHECK: 0x0 R_ARM_PREL31 .TEST2 0x0 +@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0 +@ CHECK: ] diff --git a/test/MC/ARM/eh-directive-section-multiple-func.s b/test/MC/ARM/eh-directive-section-multiple-func.s index 444099f8f6..9f632b8b89 100644 --- a/test/MC/ARM/eh-directive-section-multiple-func.s +++ b/test/MC/ARM/eh-directive-section-multiple-func.s @@ -65,14 +65,14 @@ func2: @------------------------------------------------------------------------------- @ CHECK: Section { @ CHECK: Name: .ARM.extab.TEST1 -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 -@ CHECK: 0x8 R_ARM_PREL31 __gxx_personality_v0 0x0 -@ CHECK: ] @ CHECK: SectionData ( @ CHECK: 0000: 00000000 B0B0B000 00000000 B0B0B000 |................| @ CHECK: ) @ CHECK: } +@ CHECK: Relocations [ +@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 +@ CHECK: 0x8 R_ARM_PREL31 __gxx_personality_v0 0x0 +@ CHECK: ] @------------------------------------------------------------------------------- @@ -82,6 +82,15 @@ func2: @ CHECK: Name: .ARM.exidx.TEST1 @ CHECK: Link: 4 @------------------------------------------------------------------------------- +@ The first word should be the offset to .TEST1. +@ The second word should be the offset to .ARM.extab.TEST1 +@------------------------------------------------------------------------------- +@ CHECK: SectionData ( +@ CHECK: 0000: 00000000 00000000 04000000 08000000 |................| +@ CHECK: ) +@ CHECK: } +@ CHECK: ] +@------------------------------------------------------------------------------- @ The first word of each entry should be relocated to .TEST1 section. @ The second word of each entry should be relocated to @ .ARM.extab.TESET1 section. @@ -92,16 +101,6 @@ func2: @ CHECK: 0x8 R_ARM_PREL31 .TEST1 0x0 @ CHECK: 0xC R_ARM_PREL31 .ARM.extab.TEST1 0x0 @ CHECK: ] -@------------------------------------------------------------------------------- -@ The first word should be the offset to .TEST1. -@ The second word should be the offset to .ARM.extab.TEST1 -@------------------------------------------------------------------------------- -@ CHECK: SectionData ( -@ CHECK: 0000: 00000000 00000000 04000000 08000000 |................| -@ CHECK: ) -@ CHECK: } -@ CHECK: ] - @------------------------------------------------------------------------------- diff --git a/test/MC/ARM/eh-directive-section.s b/test/MC/ARM/eh-directive-section.s index 5f5d1252f8..7c1f32ee39 100644 --- a/test/MC/ARM/eh-directive-section.s +++ b/test/MC/ARM/eh-directive-section.s @@ -60,13 +60,13 @@ func2: @------------------------------------------------------------------------------- @ CHECK: Section { @ CHECK: Name: .ARM.extab.TEST1 -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 -@ CHECK: ] @ CHECK: SectionData ( @ CHECK: 0000: 00000000 B0B0B000 |........| @ CHECK: ) @ CHECK: } +@ CHECK: Relocations [ +@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 +@ CHECK: ] @------------------------------------------------------------------------------- @@ -85,15 +85,14 @@ func2: @ The second word should be relocated to the EHTAB entry in .ARM.extab.TEST1 @ section. @------------------------------------------------------------------------------- -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 -@ CHECK: ] @ CHECK: SectionData ( @ CHECK: 0000: 00000000 00000000 |........| @ CHECK: ) @ CHECK: } - +@ CHECK: Relocations [ +@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0 +@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 +@ CHECK: ] @------------------------------------------------------------------------------- @@ -112,13 +111,13 @@ func2: @------------------------------------------------------------------------------- @ CHECK: Section { @ CHECK: Name: .ARM.extabTEST2 -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 -@ CHECK: ] @ CHECK: SectionData ( @ CHECK: 0000: 00000000 B0B0B000 |........| @ CHECK: ) @ CHECK: } +@ CHECK: Relocations [ +@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 +@ CHECK: ] @------------------------------------------------------------------------------- @@ -137,15 +136,15 @@ func2: @ The second word should be relocated to the EHTAB entry in .ARM.extabTEST2 @ section. @------------------------------------------------------------------------------- -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 TEST2 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extabTEST2 0x0 -@ CHECK: ] @ CHECK: SectionData ( @ CHECK: 0000: 00000000 00000000 |........| @ CHECK: ) @ CHECK: } @ CHECK: ] +@ CHECK: Relocations [ +@ CHECK: 0x0 R_ARM_PREL31 TEST2 0x0 +@ CHECK: 0x4 R_ARM_PREL31 .ARM.extabTEST2 0x0 +@ CHECK: ] diff --git a/test/MC/ARM/eh-directive-text-section-multiple-func.s b/test/MC/ARM/eh-directive-text-section-multiple-func.s index c9412763a8..50e09f5f11 100644 --- a/test/MC/ARM/eh-directive-text-section-multiple-func.s +++ b/test/MC/ARM/eh-directive-text-section-multiple-func.s @@ -45,14 +45,6 @@ func2: @------------------------------------------------------------------------------- @ CHECK: Section { @ CHECK: Name: .ARM.exidx -@------------------------------------------------------------------------------- -@ The first word of each entry should be relocated to .text section. -@------------------------------------------------------------------------------- -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .text 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 -@ CHECK: 0x8 R_ARM_PREL31 .text 0x0 -@ CHECK: ] @ CHECK: SectionData ( @------------------------------------------------------------------------------- @ The first word should be the offset to .text. The second word should be @@ -64,6 +56,14 @@ func2: @ CHECK: } @ CHECK: ] +@------------------------------------------------------------------------------- +@ The first word of each entry should be relocated to .text section. +@------------------------------------------------------------------------------- +@ CHECK: Relocations [ +@ CHECK: 0x0 R_ARM_PREL31 .text 0x0 +@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ CHECK: 0x8 R_ARM_PREL31 .text 0x0 +@ CHECK: ] @------------------------------------------------------------------------------- diff --git a/test/MC/ARM/eh-directive-text-section.s b/test/MC/ARM/eh-directive-text-section.s index 5ab1baa592..4a073aa811 100644 --- a/test/MC/ARM/eh-directive-text-section.s +++ b/test/MC/ARM/eh-directive-text-section.s @@ -61,16 +61,6 @@ func1: @ CHECK: Link: 1 @------------------------------------------------------------------------------- -@ The first word should be relocated to the code address in .text section. -@ Besides, since this function is using compact model 0, thus we have to -@ add an relocation to __aeabi_unwind_cpp_pr0. -@------------------------------------------------------------------------------- -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .text 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 -@ CHECK: ] - -@------------------------------------------------------------------------------- @ The first word should be the offset to .text. The second word should be @ 0xB0B0B080, which means compact model 0 is used (0x80) and the rest of the @ word is filled with FINISH opcode (0xB0). @@ -80,3 +70,13 @@ func1: @ CHECK: ) @ CHECK: } @ CHECK: ] + +@------------------------------------------------------------------------------- +@ The first word should be relocated to the code address in .text section. +@ Besides, since this function is using compact model 0, thus we have to +@ add an relocation to __aeabi_unwind_cpp_pr0. +@------------------------------------------------------------------------------- +@ CHECK: Relocations [ +@ CHECK: 0x0 R_ARM_PREL31 .text 0x0 +@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ CHECK: ] diff --git a/test/MC/ARM/elf-movt.s b/test/MC/ARM/elf-movt.s index 74b3c9f2f5..0080db4ac8 100644 --- a/test/MC/ARM/elf-movt.s +++ b/test/MC/ARM/elf-movt.s @@ -30,9 +30,29 @@ barf: @ @barf @ OBJ-NEXT: AddressAlignment: 4 @ OBJ-NEXT: EntrySize: 0 @ OBJ-NEXT: Relocations [ -@ OBJ-NEXT: 0x0 R_ARM_MOVW_PREL_NC -@ OBJ-NEXT: 0x4 R_ARM_MOVT_PREL @ OBJ-NEXT: ] @ OBJ-NEXT: SectionData ( @ OBJ-NEXT: 0000: F00F0FE3 F40F4FE3 @ OBJ-NEXT: ) +@ OBJ-NEXT: } +@ OBJ-NEXT: Section { +@ OBJ-NEXT: Index: 2 +@ OBJ-NEXT: Name: .rel.text (1) +@ OBJ-NEXT: Type: SHT_REL (0x9) +@ OBJ-NEXT: Flags [ (0x0) +@ OBJ-NEXT: ] +@ OBJ-NEXT: Address: 0x0 +@ OBJ-NEXT: Offset: 0x22C +@ OBJ-NEXT: Size: 16 +@ OBJ-NEXT: Link: 6 +@ OBJ-NEXT: Info: 1 +@ OBJ-NEXT: AddressAlignment: 4 +@ OBJ-NEXT: EntrySize: 8 +@ OBJ-NEXT: Relocations [ +@ OBJ-NEXT: 0x0 R_ARM_MOVW_PREL_NC +@ OBJ-NEXT: 0x4 R_ARM_MOVT_PREL +@ OBJ-NEXT: ] +@ OBJ-NEXT: SectionData ( +@ OBJ-NEXT: 0000: 00000000 2D060000 04000000 2E060000 |....-...........| +@ OBJ-NEXT: ) +@ OBJ-NEXT: } diff --git a/test/MC/ARM/elf-reloc-01.ll b/test/MC/ARM/elf-reloc-01.ll index 9b5dbd9e99..28be85b7db 100644 --- a/test/MC/ARM/elf-reloc-01.ll +++ b/test/MC/ARM/elf-reloc-01.ll @@ -61,7 +61,7 @@ bb3: ; preds = %bb, %entry declare void @exit(i32) noreturn nounwind ; OBJ: Relocations [ -; OBJ: Section (1) .text { +; OBJ: Section (2) .rel.text { ; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC _MergedGlobals ; OBJ: } ; OBJ: ] diff --git a/test/MC/ARM/elf-reloc-02.ll b/test/MC/ARM/elf-reloc-02.ll index f0217644ca..7eb49cc551 100644 --- a/test/MC/ARM/elf-reloc-02.ll +++ b/test/MC/ARM/elf-reloc-02.ll @@ -42,7 +42,7 @@ declare i32 @write(...) declare void @exit(i32) noreturn nounwind ;; OBJ: Relocations [ -;; OBJ: Section (1) .text { +;; OBJ: Section (2) .rel.text { ;; OBJ-NEXT: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC .L.str ;; OBJ: } ;; OBJ: ] diff --git a/test/MC/ARM/elf-reloc-03.ll b/test/MC/ARM/elf-reloc-03.ll index ac46e697c1..ee5e59eb34 100644 --- a/test/MC/ARM/elf-reloc-03.ll +++ b/test/MC/ARM/elf-reloc-03.ll @@ -89,7 +89,7 @@ entry: declare void @exit(i32) noreturn nounwind ;; OBJ: Relocations [ -;; OBJ: Section (1) .text { +;; OBJ: Section (2) .rel.text { ;; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC vtable ;; OBJ: } ;; OBJ: ] diff --git a/test/MC/ARM/elf-reloc-condcall.s b/test/MC/ARM/elf-reloc-condcall.s index 612942f2c5..a0402bdc38 100644 --- a/test/MC/ARM/elf-reloc-condcall.s +++ b/test/MC/ARM/elf-reloc-condcall.s @@ -8,7 +8,7 @@ b some_label // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rel.text { // OBJ-NEXT: 0x0 R_ARM_JUMP24 some_label 0x0 // OBJ-NEXT: 0x4 R_ARM_CALL some_label 0x0 // OBJ-NEXT: 0x8 R_ARM_CALL some_label 0x0 diff --git a/test/MC/ARM/elf-thumbfunc-reloc.ll b/test/MC/ARM/elf-thumbfunc-reloc.ll index e7d2c340d4..9fd360e1a0 100644 --- a/test/MC/ARM/elf-thumbfunc-reloc.ll +++ b/test/MC/ARM/elf-thumbfunc-reloc.ll @@ -29,7 +29,7 @@ entry: ; CHECK: ] ; CHECK: Relocations [ -; CHECK-NEXT: Section (1) .text { +; CHECK-NEXT: Section (2) .rel.text { ; CHECK-NEXT: 0x8 R_ARM_THM_CALL foo 0x0 ; CHECK-NEXT: } ; CHECK-NEXT: ] diff --git a/test/MC/ARM/elf-thumbfunc-reloc.s b/test/MC/ARM/elf-thumbfunc-reloc.s index 87a26d8df8..de3594e1ce 100644 --- a/test/MC/ARM/elf-thumbfunc-reloc.s +++ b/test/MC/ARM/elf-thumbfunc-reloc.s @@ -18,7 +18,7 @@ f: @@ make sure an R_ARM_THM_CALL relocation is generated for the call to g @CHECK: Relocations [ -@CHECK-NEXT: Section (1) .text { +@CHECK-NEXT: Section (2) .rel.text { @CHECK-NEXT: 0x4 R_ARM_THM_CALL g 0x0 @CHECK-NEXT: } @CHECK-NEXT: ] diff --git a/test/MC/ELF/alias-reloc.s b/test/MC/ELF/alias-reloc.s index c25c25932f..f5448e5ffb 100644 --- a/test/MC/ELF/alias-reloc.s +++ b/test/MC/ELF/alias-reloc.s @@ -18,7 +18,7 @@ foo2: .quad bar2 // CHECK: Relocations [ -// CHECK-NEXT: Section ({{[0-9]+}}) zed { +// CHECK-NEXT: Section ({{[0-9]+}}) .relazed { // CHECK-NEXT: 0x1 R_X86_64_PLT32 bar 0xFFFFFFFFFFFFFFFC // CHECK-NEXT: 0x5 R_X86_64_64 bar2 0x0 // CHECK-NEXT: } diff --git a/test/MC/ELF/basic-elf-32.s b/test/MC/ELF/basic-elf-32.s index 3ddb53981a..1f618e1bb6 100644 --- a/test/MC/ELF/basic-elf-32.s +++ b/test/MC/ELF/basic-elf-32.s @@ -45,7 +45,7 @@ main: # @main // CHECK: Name: .rel.text // CHECK: Relocations [ -// CHECK: Section (1) .text { +// CHECK: Section (2) .rel.text { // CHECK: 0x6 R_386_32 .rodata.str1.1 // CHECK: 0xB R_386_PC32 puts // CHECK: 0x12 R_386_32 .rodata.str1.1 diff --git a/test/MC/ELF/basic-elf-64.s b/test/MC/ELF/basic-elf-64.s index f98623ad1e..a77f3e63e0 100644 --- a/test/MC/ELF/basic-elf-64.s +++ b/test/MC/ELF/basic-elf-64.s @@ -45,7 +45,7 @@ main: # @main // CHECK: Name: .rela.text // CHECK: Relocations [ -// CHECK: Section (1) .text { +// CHECK: Section (2) .rela.text { // CHECK: 0x5 R_X86_64_32 .rodata.str1.1 0x0 // CHECK: 0xA R_X86_64_PC32 puts 0xFFFFFFFFFFFFFFFC // CHECK: 0xF R_X86_64_32 .rodata.str1.1 0x6 diff --git a/test/MC/ELF/cfi-adjust-cfa-offset.s b/test/MC/ELF/cfi-adjust-cfa-offset.s index 137b8b6f84..b3768cb983 100644 --- a/test/MC/ELF/cfi-adjust-cfa-offset.s +++ b/test/MC/ELF/cfi-adjust-cfa-offset.s @@ -26,7 +26,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -49,5 +48,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-advance-loc2.s b/test/MC/ELF/cfi-advance-loc2.s index 1cad32507c..d7a53c462b 100644 --- a/test/MC/ELF/cfi-advance-loc2.s +++ b/test/MC/ELF/cfi-advance-loc2.s @@ -24,7 +24,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -46,5 +45,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-def-cfa-offset.s b/test/MC/ELF/cfi-def-cfa-offset.s index f1a54a810e..eac2c731fa 100644 --- a/test/MC/ELF/cfi-def-cfa-offset.s +++ b/test/MC/ELF/cfi-def-cfa-offset.s @@ -25,7 +25,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -48,5 +47,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-def-cfa-register.s b/test/MC/ELF/cfi-def-cfa-register.s index b1e74ea098..00d8b99af9 100644 --- a/test/MC/ELF/cfi-def-cfa-register.s +++ b/test/MC/ELF/cfi-def-cfa-register.s @@ -21,7 +21,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -43,5 +42,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-def-cfa.s b/test/MC/ELF/cfi-def-cfa.s index abde0de4fa..36e147f5a4 100644 --- a/test/MC/ELF/cfi-def-cfa.s +++ b/test/MC/ELF/cfi-def-cfa.s @@ -21,7 +21,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -43,5 +42,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-escape.s b/test/MC/ELF/cfi-escape.s index a910faba64..839d6717de 100644 --- a/test/MC/ELF/cfi-escape.s +++ b/test/MC/ELF/cfi-escape.s @@ -22,7 +22,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -44,5 +43,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-offset.s b/test/MC/ELF/cfi-offset.s index f7f95fbc5f..951a6001e5 100644 --- a/test/MC/ELF/cfi-offset.s +++ b/test/MC/ELF/cfi-offset.s @@ -21,7 +21,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -43,5 +42,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-register.s b/test/MC/ELF/cfi-register.s index f7a07e45d8..4abbb53b8f 100644 --- a/test/MC/ELF/cfi-register.s +++ b/test/MC/ELF/cfi-register.s @@ -22,7 +22,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -44,5 +43,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-rel-offset.s b/test/MC/ELF/cfi-rel-offset.s index 35a73efb0f..34254c862a 100644 --- a/test/MC/ELF/cfi-rel-offset.s +++ b/test/MC/ELF/cfi-rel-offset.s @@ -29,7 +29,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -52,5 +51,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-rel-offset2.s b/test/MC/ELF/cfi-rel-offset2.s index 5817d1f4af..3de769f39f 100644 --- a/test/MC/ELF/cfi-rel-offset2.s +++ b/test/MC/ELF/cfi-rel-offset2.s @@ -21,7 +21,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -43,5 +42,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-remember.s b/test/MC/ELF/cfi-remember.s index 932a1828eb..98c759d4ff 100644 --- a/test/MC/ELF/cfi-remember.s +++ b/test/MC/ELF/cfi-remember.s @@ -24,7 +24,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -46,5 +45,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-restore.s b/test/MC/ELF/cfi-restore.s index 6c25d5b471..d25b5ff2e9 100644 --- a/test/MC/ELF/cfi-restore.s +++ b/test/MC/ELF/cfi-restore.s @@ -22,7 +22,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -44,5 +43,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-same-value.s b/test/MC/ELF/cfi-same-value.s index 075c6b9b84..9f5ae4be9e 100644 --- a/test/MC/ELF/cfi-same-value.s +++ b/test/MC/ELF/cfi-same-value.s @@ -22,7 +22,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -44,5 +43,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-undefined.s b/test/MC/ELF/cfi-undefined.s index c83b47c142..9773a36a3b 100644 --- a/test/MC/ELF/cfi-undefined.s +++ b/test/MC/ELF/cfi-undefined.s @@ -22,7 +22,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -44,5 +43,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/cfi-zero-addr-delta.s b/test/MC/ELF/cfi-zero-addr-delta.s index 4ac0e34f10..05cb0ae35b 100644 --- a/test/MC/ELF/cfi-zero-addr-delta.s +++ b/test/MC/ELF/cfi-zero-addr-delta.s @@ -28,7 +28,6 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 @@ -51,4 +50,5 @@ f: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 // CHECK-NEXT: ] diff --git a/test/MC/ELF/cfi.s b/test/MC/ELF/cfi.s index 98f4fa9c62..b8b6e6b52a 100644 --- a/test/MC/ELF/cfi.s +++ b/test/MC/ELF/cfi.s @@ -227,78 +227,6 @@ f36: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 -// CHECK-NEXT: 0x29 R_X86_64_32 bar 0x0 -// CHECK-NEXT: 0x43 R_X86_64_64 foo 0x0 -// CHECK-NEXT: 0x5C R_X86_64_PC32 .text 0x1 -// CHECK-NEXT: 0x65 R_X86_64_32 bar 0x0 -// CHECK-NEXT: 0x74 R_X86_64_PC32 .text 0x2 -// CHECK-NEXT: 0x7D R_X86_64_32 bar 0x0 -// CHECK-NEXT: 0x97 R_X86_64_64 foo 0x0 -// CHECK-NEXT: 0xB0 R_X86_64_PC32 .text 0x3 -// CHECK-NEXT: 0xB9 R_X86_64_16 bar 0x0 -// CHECK-NEXT: 0xCE R_X86_64_16 foo 0x0 -// CHECK-NEXT: 0xE0 R_X86_64_PC32 .text 0x4 -// CHECK-NEXT: 0xFE R_X86_64_32 foo 0x0 -// CHECK-NEXT: 0x110 R_X86_64_PC32 .text 0x5 -// CHECK-NEXT: 0x12E R_X86_64_64 foo 0x0 -// CHECK-NEXT: 0x144 R_X86_64_PC32 .text 0x6 -// CHECK-NEXT: 0x162 R_X86_64_16 foo 0x0 -// CHECK-NEXT: 0x174 R_X86_64_PC32 .text 0x7 -// CHECK-NEXT: 0x192 R_X86_64_32 foo 0x0 -// CHECK-NEXT: 0x1A4 R_X86_64_PC32 .text 0x8 -// CHECK-NEXT: 0x1C2 R_X86_64_64 foo 0x0 -// CHECK-NEXT: 0x1D8 R_X86_64_PC32 .text 0x9 -// CHECK-NEXT: 0x1F6 R_X86_64_64 foo 0x0 -// CHECK-NEXT: 0x20C R_X86_64_PC32 .text 0xA -// CHECK-NEXT: 0x22A R_X86_64_PC64 foo 0x0 -// CHECK-NEXT: 0x240 R_X86_64_PC32 .text 0xB -// CHECK-NEXT: 0x25E R_X86_64_PC16 foo 0x0 -// CHECK-NEXT: 0x270 R_X86_64_PC32 .text 0xC -// CHECK-NEXT: 0x28E R_X86_64_PC32 foo 0x0 -// CHECK-NEXT: 0x2A0 R_X86_64_PC32 .text 0xD -// CHECK-NEXT: 0x2BE R_X86_64_PC64 foo 0x0 -// CHECK-NEXT: 0x2D4 R_X86_64_PC32 .text 0xE -// CHECK-NEXT: 0x2F2 R_X86_64_PC16 foo 0x0 -// CHECK-NEXT: 0x304 R_X86_64_PC32 .text 0xF -// CHECK-NEXT: 0x322 R_X86_64_PC32 foo 0x0 -// CHECK-NEXT: 0x334 R_X86_64_PC32 .text 0x10 -// CHECK-NEXT: 0x352 R_X86_64_PC64 foo 0x0 -// CHECK-NEXT: 0x368 R_X86_64_PC32 .text 0x11 -// CHECK-NEXT: 0x386 R_X86_64_PC64 foo 0x0 -// CHECK-NEXT: 0x39C R_X86_64_PC32 .text 0x12 -// CHECK-NEXT: 0x3BA R_X86_64_64 foo 0x0 -// CHECK-NEXT: 0x3D0 R_X86_64_PC32 .text 0x13 -// CHECK-NEXT: 0x3EE R_X86_64_16 foo 0x0 -// CHECK-NEXT: 0x400 R_X86_64_PC32 .text 0x14 -// CHECK-NEXT: 0x41E R_X86_64_32 foo 0x0 -// CHECK-NEXT: 0x430 R_X86_64_PC32 .text 0x15 -// CHECK-NEXT: 0x44E R_X86_64_64 foo 0x0 -// CHECK-NEXT: 0x464 R_X86_64_PC32 .text 0x16 -// CHECK-NEXT: 0x482 R_X86_64_16 foo 0x0 -// CHECK-NEXT: 0x494 R_X86_64_PC32 .text 0x17 -// CHECK-NEXT: 0x4B2 R_X86_64_32 foo 0x0 -// CHECK-NEXT: 0x4C4 R_X86_64_PC32 .text 0x18 -// CHECK-NEXT: 0x4E2 R_X86_64_64 foo 0x0 -// CHECK-NEXT: 0x4F8 R_X86_64_PC32 .text 0x19 -// CHECK-NEXT: 0x516 R_X86_64_64 foo 0x0 -// CHECK-NEXT: 0x52C R_X86_64_PC32 .text 0x1A -// CHECK-NEXT: 0x54A R_X86_64_PC64 foo 0x0 -// CHECK-NEXT: 0x560 R_X86_64_PC32 .text 0x1B -// CHECK-NEXT: 0x57E R_X86_64_PC16 foo 0x0 -// CHECK-NEXT: 0x590 R_X86_64_PC32 .text 0x1C -// CHECK-NEXT: 0x5AE R_X86_64_PC32 foo 0x0 -// CHECK-NEXT: 0x5C0 R_X86_64_PC32 .text 0x1D -// CHECK-NEXT: 0x5DE R_X86_64_PC64 foo 0x0 -// CHECK-NEXT: 0x5F4 R_X86_64_PC32 .text 0x1E -// CHECK-NEXT: 0x612 R_X86_64_PC16 foo 0x0 -// CHECK-NEXT: 0x624 R_X86_64_PC32 .text 0x1F -// CHECK-NEXT: 0x642 R_X86_64_PC32 foo 0x0 -// CHECK-NEXT: 0x654 R_X86_64_PC32 .text 0x20 -// CHECK-NEXT: 0x672 R_X86_64_PC64 foo 0x0 -// CHECK-NEXT: 0x688 R_X86_64_PC32 .text 0x21 -// CHECK-NEXT: 0x6A6 R_X86_64_PC64 foo 0x0 -// CHECK-NEXT: 0x6BC R_X86_64_PC32 .text 0x22 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 14000000 00000000 017A4C52 00017810 @@ -427,5 +355,77 @@ f36: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: 0x29 R_X86_64_32 bar 0x0 +// CHECK-NEXT: 0x43 R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x5C R_X86_64_PC32 .text 0x1 +// CHECK-NEXT: 0x65 R_X86_64_32 bar 0x0 +// CHECK-NEXT: 0x74 R_X86_64_PC32 .text 0x2 +// CHECK-NEXT: 0x7D R_X86_64_32 bar 0x0 +// CHECK-NEXT: 0x97 R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0xB0 R_X86_64_PC32 .text 0x3 +// CHECK-NEXT: 0xB9 R_X86_64_16 bar 0x0 +// CHECK-NEXT: 0xCE R_X86_64_16 foo 0x0 +// CHECK-NEXT: 0xE0 R_X86_64_PC32 .text 0x4 +// CHECK-NEXT: 0xFE R_X86_64_32 foo 0x0 +// CHECK-NEXT: 0x110 R_X86_64_PC32 .text 0x5 +// CHECK-NEXT: 0x12E R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x144 R_X86_64_PC32 .text 0x6 +// CHECK-NEXT: 0x162 R_X86_64_16 foo 0x0 +// CHECK-NEXT: 0x174 R_X86_64_PC32 .text 0x7 +// CHECK-NEXT: 0x192 R_X86_64_32 foo 0x0 +// CHECK-NEXT: 0x1A4 R_X86_64_PC32 .text 0x8 +// CHECK-NEXT: 0x1C2 R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x1D8 R_X86_64_PC32 .text 0x9 +// CHECK-NEXT: 0x1F6 R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x20C R_X86_64_PC32 .text 0xA +// CHECK-NEXT: 0x22A R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x240 R_X86_64_PC32 .text 0xB +// CHECK-NEXT: 0x25E R_X86_64_PC16 foo 0x0 +// CHECK-NEXT: 0x270 R_X86_64_PC32 .text 0xC +// CHECK-NEXT: 0x28E R_X86_64_PC32 foo 0x0 +// CHECK-NEXT: 0x2A0 R_X86_64_PC32 .text 0xD +// CHECK-NEXT: 0x2BE R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x2D4 R_X86_64_PC32 .text 0xE +// CHECK-NEXT: 0x2F2 R_X86_64_PC16 foo 0x0 +// CHECK-NEXT: 0x304 R_X86_64_PC32 .text 0xF +// CHECK-NEXT: 0x322 R_X86_64_PC32 foo 0x0 +// CHECK-NEXT: 0x334 R_X86_64_PC32 .text 0x10 +// CHECK-NEXT: 0x352 R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x368 R_X86_64_PC32 .text 0x11 +// CHECK-NEXT: 0x386 R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x39C R_X86_64_PC32 .text 0x12 +// CHECK-NEXT: 0x3BA R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x3D0 R_X86_64_PC32 .text 0x13 +// CHECK-NEXT: 0x3EE R_X86_64_16 foo 0x0 +// CHECK-NEXT: 0x400 R_X86_64_PC32 .text 0x14 +// CHECK-NEXT: 0x41E R_X86_64_32 foo 0x0 +// CHECK-NEXT: 0x430 R_X86_64_PC32 .text 0x15 +// CHECK-NEXT: 0x44E R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x464 R_X86_64_PC32 .text 0x16 +// CHECK-NEXT: 0x482 R_X86_64_16 foo 0x0 +// CHECK-NEXT: 0x494 R_X86_64_PC32 .text 0x17 +// CHECK-NEXT: 0x4B2 R_X86_64_32 foo 0x0 +// CHECK-NEXT: 0x4C4 R_X86_64_PC32 .text 0x18 +// CHECK-NEXT: 0x4E2 R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x4F8 R_X86_64_PC32 .text 0x19 +// CHECK-NEXT: 0x516 R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x52C R_X86_64_PC32 .text 0x1A +// CHECK-NEXT: 0x54A R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x560 R_X86_64_PC32 .text 0x1B +// CHECK-NEXT: 0x57E R_X86_64_PC16 foo 0x0 +// CHECK-NEXT: 0x590 R_X86_64_PC32 .text 0x1C +// CHECK-NEXT: 0x5AE R_X86_64_PC32 foo 0x0 +// CHECK-NEXT: 0x5C0 R_X86_64_PC32 .text 0x1D +// CHECK-NEXT: 0x5DE R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x5F4 R_X86_64_PC32 .text 0x1E +// CHECK-NEXT: 0x612 R_X86_64_PC16 foo 0x0 +// CHECK-NEXT: 0x624 R_X86_64_PC32 .text 0x1F +// CHECK-NEXT: 0x642 R_X86_64_PC32 foo 0x0 +// CHECK-NEXT: 0x654 R_X86_64_PC32 .text 0x20 +// CHECK-NEXT: 0x672 R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x688 R_X86_64_PC32 .text 0x21 +// CHECK-NEXT: 0x6A6 R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x6BC R_X86_64_PC32 .text 0x22 // CHECK-NEXT: ] // CHECK: } diff --git a/test/MC/ELF/gen-dwarf.s b/test/MC/ELF/gen-dwarf.s index 907bf424f4..a702bc8610 100644 --- a/test/MC/ELF/gen-dwarf.s +++ b/test/MC/ELF/gen-dwarf.s @@ -15,11 +15,11 @@ foo: .size foo, .-foo // CHECK: Relocations [ -// CHECK: Section ({{[^ ]+}}) .debug_info { +// CHECK: Section ({{[^ ]+}}) .rel.debug_info { // CHECK-NEXT: 0x6 R_386_32 .debug_abbrev 0x0 // CHECK-NEXT: 0xC R_386_32 .debug_line 0x0 // CHECK: } -// CHECK-NEXT: Section ({{[^ ]+}}) .debug_aranges { +// CHECK-NEXT: Section ({{[^ ]+}}) .rel.debug_aranges { // CHECK-NEXT: 0x6 R_386_32 .debug_info 0x0 // CHECK-NEXT: 0x10 R_386_32 .text 0x0 // CHECK-NEXT: } diff --git a/test/MC/ELF/got.s b/test/MC/ELF/got.s index 60dea6d3b1..30114b75d8 100644 --- a/test/MC/ELF/got.s +++ b/test/MC/ELF/got.s @@ -7,7 +7,7 @@ movl foo@GOTPCREL(%rip), %eax // CHECK: Relocations [ -// CHECK: Section ({{[^ ]+}}) .text { +// CHECK: Section ({{[^ ]+}}) .rela.text { // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_GOT32 foo 0x{{[^ ]+}} // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_GOTPCREL foo 0x{{[^ ]+}} // CHECK-NEXT: } diff --git a/test/MC/ELF/local-reloc.s b/test/MC/ELF/local-reloc.s index 4241ba5af4..0c745197c8 100644 --- a/test/MC/ELF/local-reloc.s +++ b/test/MC/ELF/local-reloc.s @@ -7,7 +7,7 @@ foo: // CHECKT: Relocations [ -// CHECK: Section (1) .text { +// CHECK: Section (2) .rela.text { // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32S .text 0x{{[^ ]+}} // CHECK-NEXT: } // CHECK-NEXT: ] diff --git a/test/MC/ELF/merge.s b/test/MC/ELF/merge.s index d34635a671..0e92583192 100644 --- a/test/MC/ELF/merge.s +++ b/test/MC/ELF/merge.s @@ -23,7 +23,7 @@ zed: foo: // CHECK: Relocations [ -// CHECK-NEXT: Section (1) .text { +// CHECK-NEXT: Section (2) .rela.text { // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_PC32 .Lfoo 0x{{[^ ]+}} // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32 .sec1 0x{{[^ ]+}} // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32 .Lfoo 0x{{[^ ]+}} diff --git a/test/MC/ELF/relocation-386.s b/test/MC/ELF/relocation-386.s index 24d0172e72..9bc831056a 100644 --- a/test/MC/ELF/relocation-386.s +++ b/test/MC/ELF/relocation-386.s @@ -4,7 +4,7 @@ // correctly point to the section or the symbol. // CHECK: Relocations [ -// CHECK-NEXT: Section (1) .text { +// CHECK-NEXT: Section (2) .rel.text { // CHECK-NEXT: 0x2 R_386_GOTOFF .Lfoo 0x0 // CHECK-NEXT: 0x{{[^ ]+}} R_386_PLT32 bar2 0x0 // CHECK-NEXT: 0x{{[^ ]+}} R_386_GOTPC _GLOBAL_OFFSET_TABLE_ 0x0 diff --git a/test/MC/ELF/relocation-pc.s b/test/MC/ELF/relocation-pc.s index 551f5ff378..fc7420c398 100644 --- a/test/MC/ELF/relocation-pc.s +++ b/test/MC/ELF/relocation-pc.s @@ -9,8 +9,6 @@ // CHECK: Index: 1 // CHECK-NEXT: Name: .text // CHECK: Relocations [ -// CHECK-NEXT: 0x1 R_X86_64_PC8 - 0x0 -// CHECK-NEXT: 0x3 R_X86_64_PC32 - 0x0 // CHECK-NEXT: ] // CHECK-NEXT: } @@ -28,5 +26,7 @@ // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 24 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x1 R_X86_64_PC8 - 0x0 +// CHECK-NEXT: 0x3 R_X86_64_PC32 - 0x0 // CHECK-NEXT: ] // CHECK-NEXT: } diff --git a/test/MC/ELF/relocation.s b/test/MC/ELF/relocation.s index 19bcc18d8f..18d43dab76 100644 --- a/test/MC/ELF/relocation.s +++ b/test/MC/ELF/relocation.s @@ -21,7 +21,7 @@ bar: // CHECK: Section { -// CHECK: Name: .text +// CHECK: Name: .rela.text // CHECK: Relocations [ // CHECK-NEXT: 0x1 R_X86_64_32 .text // CHECK-NEXT: 0x8 R_X86_64_32S .text diff --git a/test/MC/ELF/rename.s b/test/MC/ELF/rename.s index c50910b41e..5364dde9f4 100644 --- a/test/MC/ELF/rename.s +++ b/test/MC/ELF/rename.s @@ -32,10 +32,27 @@ defined3: // CHECK-NEXT: AddressAlignment: 4 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 2 +// CHECK-NEXT: Name: .rela.text (1) +// CHECK-NEXT: Type: SHT_RELA (0x4) +// CHECK-NEXT: Flags [ (0x0) +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x320 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 6 +// CHECK-NEXT: Info: 1 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ // CHECK-NEXT: 0x0 R_X86_64_32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: } + // Symbol 2 is section 1 // CHECK: Symbol { // CHECK: Name: .text (0) diff --git a/test/MC/ELF/symref.s b/test/MC/ELF/symref.s index 9a71a81930..c8015b96a3 100644 --- a/test/MC/ELF/symref.s +++ b/test/MC/ELF/symref.s @@ -22,7 +22,7 @@ defined3: global1: // CHECK: Relocations [ -// CHECK-NEXT: Section (1) .text { +// CHECK-NEXT: Section (2) .rela.text { // CHECK-NEXT: 0x0 R_X86_64_32 .text 0x0 // CHECK-NEXT: 0x4 R_X86_64_32 bar2@zed 0x0 // CHECK-NEXT: 0x8 R_X86_64_32 .text 0x0 diff --git a/test/MC/ELF/weak-relocation.s b/test/MC/ELF/weak-relocation.s index 0f5bba2383..19153aa50d 100644 --- a/test/MC/ELF/weak-relocation.s +++ b/test/MC/ELF/weak-relocation.s @@ -8,7 +8,7 @@ bar: call foo // CHECK: Relocations [ -// CHECK-NEXT: Section ({{[0-9]+}}) .text { +// CHECK-NEXT: Section ({{[0-9]+}}) .rela.text { // CHECK-NEXT: 0x1 R_X86_64_PC32 foo 0xFFFFFFFFFFFFFFFC // CHECK-NEXT: } // CHECK-NEXT: ] diff --git a/test/MC/ELF/x86_64-reloc-sizetest.s b/test/MC/ELF/x86_64-reloc-sizetest.s index bd67ee0f9d..10c13123e6 100644 --- a/test/MC/ELF/x86_64-reloc-sizetest.s +++ b/test/MC/ELF/x86_64-reloc-sizetest.s @@ -7,7 +7,7 @@ L: movq $(L + 2147483648),%rax // CHECK: Relocations [ -// CHECK-NEXT: Section ({{[0-9]+}}) .text { +// CHECK-NEXT: Section ({{[0-9]+}}) .rela.text { // CHECK-NEXT: 0x3 R_X86_64_32S {{[^ ]+}} 0x80000000 // CHECK-NEXT: } // CHECK-NEXT: ] diff --git a/test/MC/Mips/eh-frame.s b/test/MC/Mips/eh-frame.s index 93ff0b8bd2..167159885d 100644 --- a/test/MC/Mips/eh-frame.s +++ b/test/MC/Mips/eh-frame.s @@ -19,7 +19,7 @@ func: .cfi_startproc .cfi_endproc -// MIPS32: RELOCATION RECORDS FOR [.eh_frame]: +// MIPS32: RELOCATION RECORDS FOR [.rel.eh_frame]: // MIPS32-NEXT: R_MIPS_32 // MIPS32: Contents of section .eh_frame: // MIPS32-NEXT: 0000 @@ -55,7 +55,7 @@ func: // MIPS32: 0b // FIXME: The instructions are different from the ones produces by gas. -// MIPS32EL: RELOCATION RECORDS FOR [.eh_frame]: +// MIPS32EL: RELOCATION RECORDS FOR [.rel.eh_frame]: // MIPS32EL-NEXT: R_MIPS_32 // MIPS32EL: Contents of section .eh_frame: // MIPS32EL-NEXT: 0000 @@ -91,7 +91,7 @@ func: // MIPS32EL: 0b // FIXME: The instructions are different from the ones produces by gas. -// MIPS64: RELOCATION RECORDS FOR [.eh_frame]: +// MIPS64: RELOCATION RECORDS FOR [.rela.eh_frame]: // MIPS64-NEXT: R_MIPS_64 // MIPS64: Contents of section .eh_frame: // MIPS64-NEXT: 0000 @@ -129,7 +129,7 @@ func: // FIXME: The instructions are different from the ones produces by gas. -// MIPS64EL: RELOCATION RECORDS FOR [.eh_frame]: +// MIPS64EL: RELOCATION RECORDS FOR [.rela.eh_frame]: // MIPS64EL-NEXT: R_MIPS_64 // MIPS64EL: Contents of section .eh_frame: // MIPS64EL-NEXT: 0000 diff --git a/test/MC/Mips/elf-gprel-32-64.ll b/test/MC/Mips/elf-gprel-32-64.ll index 47003fa1e7..4057eb823a 100644 --- a/test/MC/Mips/elf-gprel-32-64.ll +++ b/test/MC/Mips/elf-gprel-32-64.ll @@ -31,7 +31,7 @@ return: ; R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE ; CHECK: Relocations [ -; CHECK: Section ({{[a-z0-9]+}}) .rodata { +; CHECK: Section ({{[a-z0-9]+}}) .rela.rodata { ; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE ; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE ; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE diff --git a/test/MC/Mips/elf-tls.ll b/test/MC/Mips/elf-tls.ll index 9f604e00a0..bcce3d515e 100644 --- a/test/MC/Mips/elf-tls.ll +++ b/test/MC/Mips/elf-tls.ll @@ -3,7 +3,7 @@ ; Check that the appropriate relocations were created. ; CHECK: Relocations [ -; CHECK: Section (1) .text { +; CHECK: Section (2) .rel.text { ; CHECK: R_MIPS_TLS_LDM ; CHECK: R_MIPS_TLS_DTPREL_HI16 ; CHECK: R_MIPS_TLS_DTPREL_LO16 diff --git a/test/MC/PowerPC/ppc64-initial-cfa.ll b/test/MC/PowerPC/ppc64-initial-cfa.ll index 23a77384ec..490244d5af 100644 --- a/test/MC/PowerPC/ppc64-initial-cfa.ll +++ b/test/MC/PowerPC/ppc64-initial-cfa.ll @@ -24,7 +24,6 @@ entry: ; STATIC-NEXT: AddressAlignment: 8 ; STATIC-NEXT: EntrySize: ; STATIC-NEXT: Relocations [ -; STATIC-NEXT: 0x1C R_PPC64_REL32 .text 0x0 ; STATIC-NEXT: ] ; STATIC-NEXT: SectionData ( ; STATIC-NEXT: 0000: 00000010 00000000 017A5200 01784101 @@ -45,7 +44,9 @@ entry: ; STATIC-NEXT: Info: ; STATIC-NEXT: AddressAlignment: 8 ; STATIC-NEXT: EntrySize: 24 - +; STATIC-NEXT: Relocations [ +; STATIC-NEXT: 0x1C R_PPC64_REL32 .text 0x0 +; STATIC-NEXT: ] ; PIC: Section { ; PIC: Name: .eh_frame @@ -61,7 +62,6 @@ entry: ; PIC-NEXT: AddressAlignment: 8 ; PIC-NEXT: EntrySize: 0 ; PIC-NEXT: Relocations [ -; PIC-NEXT: 0x1C R_PPC64_REL32 .text 0x0 ; PIC-NEXT: ] ; PIC-NEXT: SectionData ( ; PIC-NEXT: 0000: 00000010 00000000 017A5200 01784101 @@ -82,3 +82,6 @@ entry: ; PIC-NEXT: Info: ; PIC-NEXT: AddressAlignment: 8 ; PIC-NEXT: EntrySize: 24 +; PIC-NEXT: Relocations [ +; PIC-NEXT: 0x1C R_PPC64_REL32 .text 0x0 +; PIC-NEXT: ] diff --git a/test/MC/PowerPC/ppc64-relocs-01.ll b/test/MC/PowerPC/ppc64-relocs-01.ll index ac8d303dd4..f4aa347e6c 100644 --- a/test/MC/PowerPC/ppc64-relocs-01.ll +++ b/test/MC/PowerPC/ppc64-relocs-01.ll @@ -27,7 +27,7 @@ entry: ;; The relocations in .rela.text are the 'number64' load using a ;; R_PPC64_TOC16_DS against the .toc and the 'sin' external function ;; address using a R_PPC64_REL24 -;; CHECK: Section ({{[0-9]+}}) .text { +;; CHECK: Section ({{[0-9]+}}) .rela.text { ;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_DS .toc ;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_REL24 sin ;; CHECK-NEXT: } @@ -37,12 +37,12 @@ entry: ; address itself); ;; 2. And a R_PPC64_TOC against no symbol (the linker will replace for the ;; module's TOC base). -;; CHECK: Section ({{[0-9]+}}) .opd { +;; CHECK: Section ({{[0-9]+}}) .rela.opd { ;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_ADDR64 .text 0x0 ;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC - 0x0 ;; Finally the TOC creates the relocation for the 'number64'. -;; CHECK: Section ({{[0-9]+}}) .toc { +;; CHECK: Section ({{[0-9]+}}) .rela.toc { ;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_ADDR64 number64 0x0 ;; CHECK-NEXT: } diff --git a/test/MC/PowerPC/ppc64-tls-relocs-01.ll b/test/MC/PowerPC/ppc64-tls-relocs-01.ll index 4e901e816a..ae32fa7b89 100644 --- a/test/MC/PowerPC/ppc64-tls-relocs-01.ll +++ b/test/MC/PowerPC/ppc64-tls-relocs-01.ll @@ -13,7 +13,7 @@ entry: ;; Check for a pair of R_PPC64_TPREL16_HA / R_PPC64_TPREL16_LO relocs ;; against the thread-local symbol 't'. ;; CHECK: Relocations [ -;; CHECK: Section ({{[0-9]+}}) .text { +;; CHECK: Section ({{[0-9]+}}) .rela.text { ;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA t ;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO t ;; CHECK-NEXT: } diff --git a/test/Object/relocation-executable.test b/test/Object/relocation-executable.test index 7625ec20af..1236035d9f 100644 --- a/test/Object/relocation-executable.test +++ b/test/Object/relocation-executable.test @@ -2,7 +2,15 @@ RUN: llvm-readobj -r -expand-relocs %p/Inputs/hello-world.elf-x86-64 \ RUN: | FileCheck %s // CHECK: Relocations [ -// CHECK: Section (11) .plt { +// CHECK-NEXT: Section (8) .rela.dyn { +// CHECK-NEXT: Relocation { +// CHECK-NEXT: Offset: 0x4018D8 +// CHECK-NEXT: Type: R_X86_64_GLOB_DAT (6) +// CHECK-NEXT: Symbol: __gmon_start__ +// CHECK-NEXT: Addend: 0x0 +// CHECK-NEXT: } +// CHECK-NEXT: } +// CHECK-NEXT: Section (9) .rela.plt { // CHECK-NEXT: Relocation { // CHECK-NEXT: Offset: 0x4018F8 // CHECK-NEXT: Type: R_X86_64_JUMP_SLOT (7) diff --git a/test/tools/llvm-readobj/relocations.test b/test/tools/llvm-readobj/relocations.test index dec7f86298..3a87ff548e 100644 --- a/test/tools/llvm-readobj/relocations.test +++ b/test/tools/llvm-readobj/relocations.test @@ -22,7 +22,7 @@ COFF-NEXT: } COFF-NEXT: ] ELF: Relocations [ -ELF-NEXT: Section (1) .text { +ELF-NEXT: Section (2) .rel.text { ELF-NEXT: 0xC R_386_GOTPC _GLOBAL_OFFSET_TABLE_ 0x0 ELF-NEXT: 0x12 R_386_GOTOFF .L.str 0x0 ELF-NEXT: 0x1A R_386_PLT32 puts 0x0 diff --git a/test/tools/llvm-readobj/sections-ext.test b/test/tools/llvm-readobj/sections-ext.test index 327f040854..e3a40c3eb1 100644 --- a/test/tools/llvm-readobj/sections-ext.test +++ b/test/tools/llvm-readobj/sections-ext.test @@ -108,10 +108,6 @@ ELF-NEXT: Info: 0 ELF-NEXT: AddressAlignment: 16 ELF-NEXT: EntrySize: 0 ELF-NEXT: Relocations [ -ELF-NEXT: 0xC R_386_GOTPC _GLOBAL_OFFSET_TABLE_ 0x0 -ELF-NEXT: 0x12 R_386_GOTOFF .L.str 0x0 -ELF-NEXT: 0x1A R_386_PLT32 puts 0x0 -ELF-NEXT: 0x1F R_386_PLT32 SomeOtherFunction 0x0 ELF-NEXT: ] ELF-NEXT: Symbols [ ELF-NEXT: Symbol { @@ -139,6 +135,32 @@ ELF-NEXT: 0010: 8D830000 00008904 24E8FCFF FFFFE8FC |........$.......| ELF-NEXT: 0020: FFFFFF31 C083C408 5BC3 |...1....[.| ELF-NEXT: ) ELF-NEXT: } +ELF-NEXT: Section { +ELF-NEXT: Index: 2 +ELF-NEXT: Name: .rel.text (1) +ELF-NEXT: Type: SHT_REL (0x9) +ELF-NEXT: Flags [ (0x0) +ELF-NEXT: ] +ELF-NEXT: Address: 0x0 +ELF-NEXT: Offset: 0x360 +ELF-NEXT: Size: 32 +ELF-NEXT: Link: 8 +ELF-NEXT: Info: 1 +ELF-NEXT: AddressAlignment: 4 +ELF-NEXT: EntrySize: 8 +ELF-NEXT: Relocations [ +ELF-NEXT: 0xC R_386_GOTPC _GLOBAL_OFFSET_TABLE_ 0x0 +ELF-NEXT: 0x12 R_386_GOTOFF .L.str 0x0 +ELF-NEXT: 0x1A R_386_PLT32 puts 0x0 +ELF-NEXT: 0x1F R_386_PLT32 SomeOtherFunction 0x0 +ELF-NEXT: ] +ELF-NEXT: Symbols [ +ELF-NEXT: ] +ELF-NEXT: SectionData ( +ELF-NEXT: 0000: 0C000000 0A0A0000 12000000 09020000 |................| +ELF-NEXT: 0010: 1A000000 040B0000 1F000000 04090000 |................| +ELF-NEXT: ) +ELF-NEXT: } MACHO-I386: Sections [ MACHO-I386-NEXT: Section { |