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-rw-r--r--lib/CodeGen/VirtRegRewriter.cpp3
-rw-r--r--test/CodeGen/Blackfin/2009-08-15-MissingDead.ll25
2 files changed, 28 insertions, 0 deletions
diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp
index b34d43a1f5..3e651a57cf 100644
--- a/lib/CodeGen/VirtRegRewriter.cpp
+++ b/lib/CodeGen/VirtRegRewriter.cpp
@@ -1587,6 +1587,7 @@ private:
MachineInstr *LoadMI = prior(InsertLoc);
VRM.addSpillSlotUse(SS, LoadMI);
++NumPSpills;
+ DistanceMap.insert(std::make_pair(LoadMI, Dist++));
}
NextMII = next(MII);
}
@@ -1678,6 +1679,7 @@ private:
MachineInstr *LoadMI = prior(InsertLoc);
VRM.addSpillSlotUse(SSorRMId, LoadMI);
++NumLoads;
+ DistanceMap.insert(std::make_pair(LoadMI, Dist++));
}
// This invalidates Phys.
@@ -1977,6 +1979,7 @@ private:
MachineInstr *LoadMI = prior(InsertLoc);
VRM.addSpillSlotUse(SSorRMId, LoadMI);
++NumLoads;
+ DistanceMap.insert(std::make_pair(LoadMI, Dist++));
}
// This invalidates PhysReg.
Spills.ClobberPhysReg(PhysReg);
diff --git a/test/CodeGen/Blackfin/2009-08-15-MissingDead.ll b/test/CodeGen/Blackfin/2009-08-15-MissingDead.ll
new file mode 100644
index 0000000000..656cd337aa
--- /dev/null
+++ b/test/CodeGen/Blackfin/2009-08-15-MissingDead.ll
@@ -0,0 +1,25 @@
+; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs
+
+; LocalRewriter can forget to transfer a <def,dead> flag when setting up call
+; argument registers. This then causes register scavenger asserts.
+
+declare i32 @printf(i8*, i32, float)
+
+define i32 @testissue(i32 %i, float %x, float %y) {
+ br label %bb1
+
+bb1: ; preds = %bb1, %0
+ %x2 = fmul float %x, 5.000000e-01 ; <float> [#uses=1]
+ %y2 = fmul float %y, 0x3FECCCCCC0000000 ; <float> [#uses=1]
+ %z2 = fadd float %x2, %y2 ; <float> [#uses=1]
+ %z3 = fadd float undef, %z2 ; <float> [#uses=1]
+ %i1 = shl i32 %i, 3 ; <i32> [#uses=1]
+ %j1 = add i32 %i, 7 ; <i32> [#uses=1]
+ %m1 = add i32 %i1, %j1 ; <i32> [#uses=2]
+ %b = icmp sle i32 %m1, 6 ; <i1> [#uses=1]
+ br i1 %b, label %bb1, label %bb2
+
+bb2: ; preds = %bb1
+ %1 = call i32 @printf(i8* undef, i32 %m1, float %z3); <i32> [#uses=0]
+ ret i32 0
+}