diff options
| -rw-r--r-- | lib/Target/X86/X86FastISel.cpp | 18 | ||||
| -rw-r--r-- | test/CodeGen/X86/fast-isel.ll | 9 |
2 files changed, 24 insertions, 3 deletions
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 5e9a39f056..a184c3995d 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -195,6 +195,7 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, const TargetRegisterClass *RC = NULL; switch (VT.getSimpleVT().SimpleTy) { default: return false; + case MVT::i1: case MVT::i8: Opc = X86::MOV8rm; RC = X86::GR8RegisterClass; @@ -252,6 +253,14 @@ X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, switch (VT.getSimpleVT().SimpleTy) { case MVT::f80: // No f80 support yet. default: return false; + case MVT::i1: { + // Mask out all but lowest bit. + unsigned AndResult = createResultReg(X86::GR8RegisterClass); + BuildMI(MBB, DL, + TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1); + Val = AndResult; + } + // FALLTHROUGH, handling i1 as i8. case MVT::i8: Opc = X86::MOV8mr; break; case MVT::i16: Opc = X86::MOV16mr; break; case MVT::i32: Opc = X86::MOV32mr; break; @@ -277,8 +286,10 @@ bool X86FastISel::X86FastEmitStore(EVT VT, Value *Val, // If this is a store of a simple constant, fold the constant into the store. if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) { unsigned Opc = 0; + bool Signed = true; switch (VT.getSimpleVT().SimpleTy) { default: break; + case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8. case MVT::i8: Opc = X86::MOV8mi; break; case MVT::i16: Opc = X86::MOV16mi; break; case MVT::i32: Opc = X86::MOV32mi; break; @@ -291,7 +302,8 @@ bool X86FastISel::X86FastEmitStore(EVT VT, Value *Val, if (Opc) { addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM) - .addImm(CI->getSExtValue()); + .addImm(Signed ? CI->getSExtValue() : + CI->getZExtValue()); return true; } } @@ -606,7 +618,7 @@ bool X86FastISel::X86SelectCallAddress(Value *V, X86AddressMode &AM) { /// X86SelectStore - Select and emit code to implement store instructions. bool X86FastISel::X86SelectStore(Instruction* I) { EVT VT; - if (!isTypeLegal(I->getOperand(0)->getType(), VT)) + if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true)) return false; X86AddressMode AM; @@ -620,7 +632,7 @@ bool X86FastISel::X86SelectStore(Instruction* I) { /// bool X86FastISel::X86SelectLoad(Instruction *I) { EVT VT; - if (!isTypeLegal(I->getType(), VT)) + if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true)) return false; X86AddressMode AM; diff --git a/test/CodeGen/X86/fast-isel.ll b/test/CodeGen/X86/fast-isel.ll index a9a016b7d0..8d6ddb4dbe 100644 --- a/test/CodeGen/X86/fast-isel.ll +++ b/test/CodeGen/X86/fast-isel.ll @@ -64,3 +64,12 @@ define i8* @inttoptr_i32(i32 %p) nounwind { %t = inttoptr i32 %p to i8* ret i8* %t } + +define void @store_i1(i1* %p, i1 %t) nounwind { + store i1 %t, i1* %p + ret void +} +define i1 @load_i1(i1* %p) nounwind { + %t = load i1* %p + ret i1 %t +} |