diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 6 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll | 10 |
2 files changed, 14 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 4650ad720c..4225ada887 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3399,8 +3399,10 @@ SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, // If this value is in the range [-32,30] and is even, use: // tmp = VSPLTI[bhw], result = add tmp, tmp if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { - Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); - return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); + SDOperand Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG); + Res = DAG.getNode(ISD::ADD, Res.getValueType(), Res, Res); + return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); + } // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is diff --git a/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll b/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll new file mode 100644 index 0000000000..b6b9c89730 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vadduhm +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsubuhm + +define <4 x i32> @test() nounwind { + ret <4 x i32> < i32 4293066722, i32 4293066722, i32 4293066722, i32 4293066722> +} + +define <4 x i32> @test2() nounwind { + ret <4 x i32> < i32 1114129, i32 1114129, i32 1114129, i32 1114129> +} |